User's Manual

Clocking
4-4 Intel
®
820 Chipset Design Guide
Figure 4-2 shows the Intel
®
820 chipset clock length routing guidelines.
Figure 4-2. Intel
®
820 Chipset Clock Routing Guidelines
1,2
Note:
1. Tie 3V66 clock for the MCH to 3V66 clock for the AGP connector to eliminate pin-to-pin skew.
2. These calculations based on 150ps/in trace velocity.
3. The TBD value will be derived from the PCI Revision 2.2 Specification which allows for a maximum of ±2ns
clock skew.
CPUCLK to MCH
Y
CPUCLK to SC242
Note: Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin-to-pin skew.
±0"
Y
5.3"
3V66 Clock for
MCH and ICH
±0"
4"Z
PCI Clock for ICH
±0"
4"Z
PCI Clock for On-Board
Devices (excluding ICH)
±TBD
3
4"Z
3V66 Clock for
AGP Slot
Z
PCI Clock for
PCI Slots
±TBD
3
1.5"Z
820 lk t d