User's Manual

Intel
®
820 Chipset Design Guide 4-3
Clocking
NOTES:
1. DP Only
2. UP: MCH and CPU clock drivers are tied together to eliminate pin-to-pin skew. –175 and +175 pin-to-pin
skew only apply to DP.
3. UP Only
4. Clock drivers tied together to eliminate pin-to-pin skew.
5. The skew between any PCICLK clocks on any two inputs in the system.
6. The skew between any APIC clocks on any two inputs in the system.
7. If SSC is enabled, an additional
±
40ps must is added to the pin-to-pin skew
8. If SSC is enabled, an additional
±
60ps must is added to the pin-to-pin skew
Table 4-2. Intel
®
820 Chipset Platform Clock Skews
Clock Symbols
See Figure 4-1
Relationship
Skew
Notes
Pin-to-Pin
(ps)
Board
(ps)
Total
(ps)
MinMaxMinMaxMinMax
A leads C,
A leads E
(or C leads E)
SC242 HCLK to SC242
HCLK (DP ONLY)
And
SC242 HCLK to MCH
HCLK (DP ONLY)
-175 +175 -125 +125 -300 +300 1, 7
A leads E
SC242 HCLK to MCH
HCLK (UP ONLY)
0 0 -125 +125 -125 +125 2, 3, 7
P leads F
MCH CLK66 to AGP
graphics device
AGPCLK
0 0 -125 +125 -125 +125 4, 8
L leads another L
(or L leads H)
PCICLK to PCICLK -500 +500 -1500 [phone] +2000
I leads H
ICH CLK66 leads ICH
PCICLK
+1500 +4000 -500 +500 +1000 +4500
F leads I
ICH CLK66 to MCH
CLK66
-250 250 -125 +125 -375 +375 8
Worst case skew
between H, L, M
and N
Worst case FWHCLK,
LPCCLK, PCICLK
-500 +500 -1500 [phone] +2000 5
B leads D,
B leads G
Processor PICCLK leads
Processor PICCLK
And
Processor PICCLK leads
ICH APICCLK
-250 +250 -125 +125 -375 +375 6