User's Manual

Intel
®
820 Chipset Design Guide 3-15
Advanced System Bus Design
double counting. T
REF
is defined as the time that it takes for the driver output pin to reach the
measurement voltage, V
REF
, starting from the beginning of the driver transition at the pad. T
REF
must be generated using the same test load for T
CO
. Intel provides this timing value in the AGTL+
I/O buffer models.
In this manner, the following valid delay equation is satisfied:
Equation 3-5. Valid Delay Equation
Valid Delay = T
CO
+ T
FLIGHT-SYS
- T
REF
= T
CO-MEASURED
+ T
FLIGHT-MEASURED
This valid delay equation is the total time from when the driver sees a valid clock pulse to the time
when the receiver sees a valid data input.
3.2.6.3 Flight Time Hardware Validation
When a measurement is made on the actual system, T
CO
and flight time do not need T
REF
correction since these are the actual numbers. These measurements include all of the effects
pertaining to the driver-system interface and the same is true for the T
CO
. Therefore the addition of
the measured T
CO
and the measured flight time must be equal to the valid delay calculated above.
3.3 Theory
3.3.1 AGTL+
AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave
switching, open-drain bus with external pull-up resistors that provide both the high logic level and
termination at each load. The processor AGTL+ drivers contain a full-cycle active pull-up device
to improve system timings. The AGTL+ specification defines:
•
Termination voltage (V
TT
).
•
Receiver reference voltage (V
REF
) as a function of termination voltage (V
TT
).
•
processor termination resistance (R
TT
).
•
Input low voltage (V
IL
).
•
Input high voltage (V
IH
).
•
NMOS on resistance (R
ON
N
).
•
PMOS on resistance (R
ON
P
).
•
Edge rate specifications.
•
Ringback specifications.
•
Overshoot/Undershoot specifications.
•
Settling Limit.