User's Manual

Advanced System Bus Design
3-14 Intel
®
820 Chipset Design Guide
3.2.6 Validation
Build systems and validate the design and simulation assumptions.
3.2.6.1 Measurements
Note that the AGTL+ specification for signal quality is at the pad of the component. The expected
method of determining the signal quality is to run analog simulations for the pin and the pad. Then
correlate the simulations at the pin against actual system measurements at the pin. Good correlation
at the pin leads to confidence that the simulation at the pad is accurate. Controlling the temperature
and voltage to correspond to the I/O buffer model extremes should enhance the correlation between
simulations and the actual system.
3.2.6.2 Flight Time Simulation
As defined in Section 3.1, “Terminology and Definitions” on page 3-1, flight time is the time
difference between a signal crossing V
REF
at the input pin of the receiver, and the output pin of the
driver crossing V
REF
were it driving a test load. The timings in the tables and topologies discussed
in this guideline assume the actual system load is 50 Ω and is equal to the test load. While the DC
loading of the AGTL+ bus in a DP mode is closer to 25 Ω, AC loading is approximately 29 Ω since
the driver effectively “sees” a 56 Ω termination resistor in parallel with a 60 Ω transmission line on
the cartridge.
Figure 3-3 above shows the different configurations for T
CO
testing and flight time simulation. The
flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. T
CO
timings are
specified at the driver pin output. T
FLIGHT-SYSTEM
is usually reported by a simulation tool as the
time from the driver pad starting its transition to the time when the receiver’s input pin sees a valid
data input. Since both timing numbers (T
CO
and T
FLIGHT-SYSTEM
) include propagation time from
the pad to the pin, it is necessary to subtract this time (T
REF
) from the reported flight time to avoid
Figure 3-3. Test Load vs. Actual System Load
V
TT
Q
Q
SET
CLR
D
Vcc
CLK
R
TEST
Test Load
Driver
Pin
Driver
Pad
T
REF
T
CO
I/O Buffer
Q
Q
SET
CLR
D
Vcc
CLK
Driver
Pad
T
FLIGHTSYSTEM
I/O Buffer
V
TT
R
TT
Actual
System
Load
Receiver
Pin