User's Manual

Advanced System Bus Design
3-12 Intel
®
820 Chipset Design Guide
3.2.4.3 Host Clock Routing
Host clock nets should be routed as point-to-point connections through a series resistor placed as
close to the output pins of the clock driver as possible. The value of the series resistor is dependent
on the clock driver characteristic impedance. However, a value of 33 Ω is a good starting point.
Table 3-5 provides the trace length recommendations for this topology. “H” indicates the length of
the host clock trace starting from the clock driver output pin and ending at the SC242 connector
BCLK pin. Note that the clock route from the clock driver to the Intel 82820 MCH will require an
additional trace length of approximately 4.6” to compensate for the additional propagation delay
along the processor host clock path (SC242 connector plus processor cartridge trace). This value of
4.6” assumes a propagation speed of 180 ps/in.
3.2.4.4 APIC Data Bus Routing
Intel recommends using the in-line topology shown in Figure 3-1 and Figure 3-2 for the APIC Data
signals, PICD[1:0]. For dual-processor systems, the network should be dual-end terminated with
330 Ω resistors. The combined routing lengths of L1 plus L2 should be between 0.0” and 12.0”.
Table 3-5. Host Clock Routing
Clock Net Trace length
Clock driver to SC242 connector H
Clock driver to Intel 82820 MCH
H + (clock delay from the processor edge to core) +
connector delay
Figure 3-1. PICD[1,0] Uni-Processor Topology
Figure 3-2. PICD[1,0] Dual-Processor Topology
Intel
®
820
Chipset
SC242
L1 < 8"
L(1):
Z0=60
Ω
±15%.
PICD[1,0]
2.5V
150 Ω
Intel
®
820
Chipset:
ICH
SC242
L1 + L2 < 12"
L(1):
Z0=60
Ω
±15%.
PICD[1,0]
2.5V
330
Ω
SC242
2.5V
330
Ω
L1
L2