User's Manual

Advanced System Bus Design
3-4 Intel
®
820 Chipset Design Guide
3.2 AGTL+ Design Guidelines
The following step-by-step guideline was developed for systems based on two processor loads and
one Intel 82820 MCH load. Systems using custom chipsets will require timing analysis and analog
simulations specific to those components.
The guideline recommended in this section is based on experience developed at Intel while
developing many different Intel Pentium
®
Pro processor family and Intel Pentium III processor-
based systems. Begin with an initial timing analysis and topology definition. Perform pre-layout
analog simulations for a detailed picture of a working “solution space” for the design. These pre-
layout simulations help define routing rules prior to placement and routing. After routing, extract
the interconnect database and perform post-layout simulations to refine the timing and signal
integrity analysis. Validate the analog simulations when actual systems become available. The
validation section describes a method for determining the flight time in the actual system.
Guideline Methodology:
•
Initial Timing Analysis
•
Determine General Topology, Layout, and Routing
•
Pre-Layout Simulation
— Sensitivity sweep
— Monte Carlo Analysis
•
Place and Route Board
— Estimate Component to Component Spacing for AGTL+ Signals
— Layout and Route Board
•
Post-Layout Simulation
— Interconnect Extraction
— Inter-Symbol Interference (ISI), Cross-talk, and Monte Carlo Analysis
•
Validation
—Measurements
— Determining Flight Time