User's Manual

Intel
®
820 Chipset Design Guide 3-1
Advanced System Bus Design
Advanced System Bus Design
3
Section 2.9, “System Bus Design” on page 2-46 describes the recommendations for designing
Intel
®
820 chipset based platforms. This chapter discusses more detail about the methodology used
to develop the guidelines. Section 3.2, “AGTL+ Design Guidelines” on page 3-4 discusses specific
system guidelines. This is a step-by-step methodology that Intel has successfully used to design
high performance desktop systems. Section 3.3, “Theory” on page 3-15 introduces the theories that
are applicable to this layout guideline. Section 3.4, “More Details and Insight” on page 3-19
contains more details and insights. The items in Section 3.4 expand on some of the rationale for the
recommendations in the step-by-step methodology. This section also includes equations that may
be used for reference.
3.1 Terminology and Definitions
Term Definition
Aggressor A network that transmits a coupled signal to another network is called the
aggressor network.
AGTL+ The processor system bus uses a bus technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain and require pull-up
resistors for providing the high logic level and termination. The processor
AGTL+ output buffers differ from GTL+ buffers with the addition of an active
pMOS pull-up transistor to “assist” the pull-up resistors during the first clock of
a low-to-high voltage transition. Additionally, the processor Single Edge
Connector (S.E.C.) cartridge contains 56 Ω pull-up resistors to provide
termination at each bus load.
Bus Agent A component or group of components that, when combined, represent a single
load on the AGTL+ bus.
Corner Describes how a component performs when all parameters that could impact
performance are adjusted to have the same impact on performance. Examples of
these parameters include variations in manufacturing process, operating
temperature, and operating voltage. The results in performance of an electronic
component that may change as a result of corners include (but are not limited
to): clock to output time, output driver edge rate, output drive current, and input
drive current. Discussion of the “slow” corner would mean having a component
operating at its slowest, weakest drive strength performance. Similar discussion
of the “fast” corner would mean having a component operating at its fastest,
strongest drive strength performance. Operation or simulation of a component at
its slow corner and fast corner is expected to bound the extremes between
slowest, weakest performance and fastest, strongest performance.