User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Setup
- 2.1 Chassis cover
- 2.2 Air ducts
- 2.3 Central Processing Unit (CPU)
- 2.4 System memory
- 2.5 Storage devices
- 2.6 Expansion slots
- 2.6.1 Installing an expansion card to the front PCIe riser card bracket (on select models)
- 2.6.2 Installing an ASUS PIKE II card
- 2.6.3 Installing an HBA/RAID card
- 2.6.4 Installing an expansion card to the rear left PCIe expansion card bracket (on select models)
- 2.6.5 Installing an expansion card to the rear right PCIe expansion card bracket (on select models)
- 2.6.6 Installing an OCP 3.0 card to the rear right OCP 3.0 socket board (on select models)
- 2.6.7 (optional) Installing the PFR module
- 2.7 Cable connections
- 2.8 Removable/optional components
- 2.9 Installing GPU cards
- 2.10 Installing Optional Kits
- Chapter 3: BIOS Setup
- 3.1 Managing and updating your BIOS
- 3.2 BIOS setup program
- 3.3 Main menu
- 3.4 Performance Tuning menu
- 3.5 Advanced menu
- 3.5.1 Trusted Computing
- 3.5.2 PSP Firmware Versions
- 3.5.3 Redfish Host Interface Settings
- 3.5.4 AMD CBS
- 3.5.5 APM Configuration
- 3.5.6 Serial Port Console Redirection
- 3.5.7 CPU Configuration
- 3.5.8 PCI Subsystem Settings
- 3.5.9 USB Configuration
- 3.5.10 Network Stack Configuration
- 3.5.11 CSM Configuration
- 3.5.12 NVMe Configuration
- 3.5.13 SATA Configuration
- 3.5.14 AMD Mem Configuration Status
- 3.5.15 Tls Auth Configuration
- 3.6 Chipset menu
- 3.7 Security menu
- 3.8 Boot menu
- 3.9 Tool menu
- 3.10 Save & Exit menu
- 3.11 Event Logs menu
- 3.12 Server Mgmt menu
- Chapter 4: Driver Installation
- Appendix
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ASUS ESC8000A-E11
Target Static Lane Select ECC [0]
Static Lane Select for ECC Lanes. The bit mask represents the bits to
be read.
Configuration options: [0] - [9]
Target Static Lane Value [0]
Configuration options: [0] - [9]
Worst Case Margin Granularity [Per Chip Select]
Configuration options: [Per Chip Select] [Per Nibble]
Read Voltage Sweep Step Size [1]
This option determines the step size for Read Data Eye voltage sweep.
Configuration options: [1] [2] [4]
Read Timing Sweep Step Size [1]
This option supports step size for Read Data Eye.
Configuration options: [1] [2] [4]
Write Voltage Sweep Step Size [1]
This option determines the step size for write Data Eye voltage sweep.
Configuration options: [1] [2] [4]
Write Timing Sweep Step Size [1]
This option supports step size for write Data Eye.
Configuration options: [1] [2] [4]
Memory Healing BIST [Disabled]
Allows you to enable a full memory test. The testing will increase the boot time.
BIOS mem BIST tests the full memory after training. Failing memory will be
repaired using soft or hard PPR depending on the PPC configuration. The test
will take 3 minutes per 16GN of installed memory. Self-Healing BIST runs the
JEDEC DRAM self healing if the device supports the feature. The DRAM will
do a hard repair for failing memory. The test will take 10 seconds per memory
rank per channel.
Configuration options: [Disabled] [BIOS Mem BIST] [Self-Healing Mem BIST]
[PMU Mem BIST] [BIOS and Self-Healing Mem BIST] [BIOS and PMU Mem
BIST] [PMU and Self-Healing Mem BIST] [BIOS and PMU Self-Healing Mem
BIST]
The following items are available only when Memory Healing BIST is set to [BIOS Mem
BIST] or [BIOS and Self-Healing Mem BIST].
Mem BIST Test Select [Vendor Tests Enabled]
Select the vendor specific tests to use with BIOS memory healing BIST.
Configuration options: [Vendor Tests Enabled] [Vendor Tests Disabled] [All
Tests - All Vendors]
Mem BIST Post Package Repair Type [Soft Repair]
For DRAM errors found in the BIOS memory BIST select the repair type, soft,
hard, or test only and do not attempt to repair.
Configuration options: [Soft Repair] [Hard Repair] [No Repairs - Test only]
The following items are available only when Memory Healing BIST is set to [PMU Mem
BIST], [BIOS and PMU Mem BIST], [PMU and Self-Healing Mem BIST] or [BIOS and
PMU and Self-Healing Mem BIST].