User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Setup
- Chapter 3: BIOS Setup
- 3.1 Managing and updating your BIOS
- 3.2 BIOS setup program
- 3.3 Main menu
- 3.4 Performance Tuning menu
- 3.5 Advanced menu
- 3.5.1 Trusted Computing
- 3.5.2 PSP Firmware Versions
- 3.5.3 Redfish Host Interface Settings
- 3.5.4 AMD CBS
- 3.5.5 APM Configuration
- 3.5.6 Onboard LAN Configuration
- 3.5.7 Serial Port Console Redirection
- 3.5.8 CPU Configuration
- 3.5.9 PCI Subsystem Settings
- 3.5.10 USB Configuration
- 3.5.11 Network Stack Configuration
- 3.5.12 CSM Configuration
- 3.5.13 NVMe Configuration
- 3.5.14 AMD Mem Configuration Status
- 3.5.15 Third-party UEFI driver configurations
- 3.6 Chipset menu
- 3.7 Security menu
- 3.8 Boot menu
- 3.9 Tool menu
- 3.10 Event Logs menu
- 3.11 Server Mgmt menu
- 3.12 Exit menu
- Chapter 4: Driver Installation
- Appendix
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ASUS ESC N4A-E11
LCLK Frequency Control
Root Complex 0x00 LCLK Frequency [Auto]
Set Root Complex LCLK Frequency (Bus range 0x00-0x3F).
[Auto] Dynamic Frequency Control (Enhanced PIO setting will be
in effect).
[593MHz] Set LCLK Frequency at 593MHz (Overrides Enhanced PIO
setting).
Root Complex 0x40 LCLK Frequency [Auto]
Set Root Complex LCLK Frequency (Bus range 0x40-0x7F).
[Auto] Dynamic Frequency Control (Enhanced PIO setting will be
in effect).
[593MHz] Set LCLK Frequency at 593MHz (Overrides Enhanced PIO
setting).
Root Complex 0x80 LCLK Frequency [Auto]
Set Root Complex LCLK Frequency (Bus range 0x80-0xBF).
[Auto] Dynamic Frequency Control (Enhanced PIO setting will be
in effect).
[593MHz] Set LCLK Frequency at 593MHz (Overrides Enhanced PIO
setting).
Root Complex 0xC0 LCLK Frequency [Auto]
Set Root Complex LCLK Frequency (Bus range 0xC0-0xFF).
[Auto] Dynamic Frequency Control (Enhanced PIO setting will be
in effect).
[593MHz] Set LCLK Frequency at 593MHz (Overrides Enhanced PIO
setting).
DF PState Mode Select [Auto]
[Normal] Normal
[Limit Highest] FCLK is limited to DF Pstate FCLK Limit, only the highest DF
Pstate is used.
[Limit All] FCLK is limited to DF Pstate FCLK limit, all DF Pstates are
used.
[Auto] Auto
The following item appears only when DF PState Mode Select is set to [Limit Highest] or
[Limit All].
DF PState FClk Limit [Auto]
Allows you to set the fixed PState when DF PState Mode Select is overridden.
Configuration options: [1600 MHz] [1467 MHz] [1333 MHz] [1200 MHz] [1067
MHz] [933 MHz] [800 MHz] [Auto]
EDC Control [Auto]
[Auto] Use the fused VDDCR_CPU EDC limit.
[Manual] User can set customized VDDCR_CPU EDC limit.