User’s Manual
Table Of Contents
26
.DDR5(
•
x x x
x x
x
DIMM_B2
DIMM_B1
DIMM_A2
DIMM_A1
1
st
DIMM_B2
DIMM_B1
DIMM_A2
DIMM_A1
1
st
DIMM_A2
DIMM_B2
DIMM_A1
DIMM_A2
DIMM_A1
DIMM_A2
DIMM_B2
DIMM_A2
DIMM_B1
DIMM_B2