User guide

Viglen Genie Executive pBTX 915 User Guide V1.0
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Intel(R) SpeedStep(tm) Tech. [Automatic]
Enable/Disable Intel Speed Step Support in BIOS. Configuration options: [Automatic]
[Disabled]
Chipset
The Chipset menu allows you to change the advanced chipset settings. Select an
item then press <Enter> to display the sub-menu.
Figure 61: Chipset Settings Screen
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. Configuration options:
[Disabled] [Enabled]
Note: The following sub-items appear when Configure DRAM Timing by SPD item is
disabled.
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time the data
actually becomes available. Configuration options: [6 Clocks] [5 Clocks] [4 Clocks] [3
Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR SDRAM.
Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and the read/write
command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6
Clocks]
DRAM RAS# Activate to Prec [15 Clocks]
Configuration options: [4 Clocks] ~ [18 Clocks]