User manual

MEX ASPERA-3
Ref.:
ME-ASP-MA-0002
Issue:
Issue 1 Rev. 4
Date:
15/2/2002
Page:
Page 6 of 58
ASPERA-3 EGSE User Manual
IFSI
CNR
1.1 SCOE
The SCOE module is responsible for command sequence generation and housekeeping data display.
This module, during the instrument level tests, is connected to MEXILT using the same (Internet
domain stream socket) protocol used by CCS in order to be used with only minor modifications at
system level test. At system level test this module is connected to CCS.
1.2 MEXILT
The MEXILT module is connected to the ASPERA instrument through a S/C simulator board, which
provide the OBDH hardware interface. The MEXILT module provides the basic OBDH-CCS emulation
and is responsible for TLM/TLC serialization, verification and transmission, and is command controlled
by the SCOE module linked via TCP/IP connection. Due to this inter process communication scheme,
the two program modules may run on different computers connected to Internet.
1.3 S/C simulator
The S/C simulator is designed around the TI 320C54x DSKplus board plus a simple external electronic
board for signal generation and OBDH compliant interfaces.
The main characteristics of the TI 320C54x board (shown in fig 5.1.2-2) are:
• One TMS320C542 ('C542) 40 MHz enhanced fixed-point DSP
• 40 MIPS (25-ns instruction cycle time)
• 10K words of dual-access RAM (DARAM)
• 2K words boot ROM
• One time-division-multiplexed (TDM) serial port
• One buffered serial port (BSP)
• One host port interface (HPI) for PC-to-DSP communications
• One on-chip timer
• Programmable, voice-quality TLC320AC01 (DAC, ADC interface circuit)
• I/O expansion bus and control signals for external designs