Product manual

Maintenance, Test and maintenance software
Technical Product Manual - DCT1800-GAP
TD 92093 (1/LZBNB 103 108 R4D) / 2006-03-09/ Ver.C
© 2006
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the test result is positive, the board controllers and peripherals will get status AVE, available. Base
stations for which no delay value is programmed yet will get the status NEW. Erroneous boards or
peripherals will get status MFG (malfunctioning).
Watchdog test
Board Controllers (BC) and controllers within base stations have a so called watchdog circuit, which
resets the controller when running in an infinite loop. The watchdog test is a test initiated by the CPU
asking all controllers to test their watchdog circuit. The processor is forced to run in a loop, after which
the watchdog circuit should reset the processor again. The watchdog on the CPU board is never tested.
2.3.2 Ack test
The Ack test is a periodic test by which the CPU sends a message to all micro processors in the
system. Each processor shall respond with an acknowledgment. If a processor is not responding, an
error is detected, and T&M will start a verification test. The test runs at default every 2 minutes. The
Ack test does not influence the system service. By means of CSM the periodic running of the Ack test
can be stopped or started and the test interval time can be changed.
2.3.3 24-hour test
The 24-hour test is a periodic system test that runs once every 24 hours. The test is similar to the
power-on test, but now all tests run under supervision of the CPU (T&M) instead of the board
controllers. Excluded from the 24-h test are boards or peripherals occupied in call handling. T&M will
wait for them to become free, while prohibiting new involvement in calls. These circuits will get status
TMT, Test Mode awaiTing. Circuits that are free from call handling are blocked immediately. Circuits
that are being tested will get status TME (Test ModE).
The system test reduces the system service noticeably. Boards or peripherals will be temporarily taken
out of service during the test or while waiting to be tested. The test should therefore run after office
hours. The default start time is 01:20 hour at night. By means of CSM the start time can be changed,
or the periodic running of the 24H test can be stopped.
2.4 Resets
In the DCT1800-GAP system, different type of resets can be generated each caused by different
actions and with different results on reset counters and error tables. Table
1 shows the relation between
action, reset type and result on counters.
2.4.1 Reset types
CPU power-on reset
A CPU power-on reset is generated when:
• The system is switched on.
• The CPU reset button is pressed.
As a result a board power-on test is started through the entire system.
Board power-on reset
A board power-on reset is generated when:
• The system is switched on.
• The CPU reset button is pressed.