Specifications

15 Signametrics
Polarity Frequency range Resolution Width range Typical
Uncertainty
Positive or negative pulse
widths
1 Hz to 100 kHz
2 µs 2 µs to 1 s 0.01 +/- 4 µs
2.9.5 Totalizer
• Active edge polarity: Positive or negative transition
• Maximum count: 10^9
• Allowed rate: 1 to 30,000 events per second
•
Uses Threshold DAC
2.10 Trigger Functions
2.10.1 External Hardware Trigger (at DIN-7 connector)
Trigger Input voltage level range High: +3V to +15V, Low: -15V to +0.8V
Ttrigger High current drive Min. 1mA, Max 10mA (TTL or CMOS logic level)
Timing Characteristics Trigger occurs within 2/Reading rate
Trigger Activation Positive or Negative edge depending on trigger
command.
Internal Reading Buffer Up to 1,000 readings/sec into 64 locations reading buffer
Isolation of trigger input ±50 V from analog DMM inputs, and from computer
chassis earth ground.
2.10.2 PXI Bus Hardware Trigger Inputs (at PXI J2)
Trigger Input TTL or CMOS positive pulse
Trigger Pulse Width
Minimum 250µS
Internal Reading Buffer up to 1,000 readings/sec into 64 readings buffer
Selectable lines PXI_TRIG1,2,3,4,5,6,7 and PXI_STAR
Isolation from DMM inputs ±330 V from any of the DMM 4 main inputs terminals
2.10.3 PXI Bus Hardware Trigger Output (to PXI J2)
Trigger Output TTL or CMOS negative pulse. Positive edge = ready
Trigger Pulse Width
Approximately 140µS
Activity A single pulse is issued for each A/D conversion (at 10
or higher measurement rate)
Selectable lines PXI_TRIG1,2,3,4,5,6 and PXI_STAR
Isolation from DMM inputs ±330 V from any of the DMM 4 main inputs terminals
2.10.4 Analog Threshold Trigger
• Captures up to 64 readings
• Reading rate: 10 rps or higher
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