Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
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MVME2502 provides two 10/100/1000 Ethernet interfaces on the front panel and another two
are routed to the RTM through the backplane connector. Due to controller limitations, one
controller is designed to be routed to the front panel or to the RTM. This setting is possible by
using a third party gigabit Ethernet LAN switch with a single enable switch such as PERICOM’s
P13L301D. The routing direction can be configured through the on-board dip switch.
The registers of the PHY can be accessed through the processor’s two-wire Ethernet
management interface.The front panel RJ45 connector has integrated speed and activity
status indicator LEDs. Isolation transformers are provided onboard for each port.
4.6 SPI Bus Interface
The enhanced serial peripheral interface (eSPI) allows the device to exchange data with
peripheral devices such as EEPROMs, RTC, Flash and the like. The eSPI is a full-duplex
synchronous, character-oriented channel that supports a simple interface such as receive,
transmit, clock and chip selects. The eSPI receiver and transmitter each have a FIFO of 32 Bytes.
P2020 supports up to four chip selects and RapidS full clock cycle operation. It can operate
both full-duplex and half duplex. It works with a range from 4-bit to 16-bit data characters and
is a single-master environment. MVME2502 is configured such that the eSPI can operate up to
200 MHz clock rate and can support booting process.The firmware boot flash resides in the
P2020 eSPI bus interface.
4.6.1 SPI Flash Memory
The MVME2502 has two 8 MB onboard serial flash. Both contain the ENV variables and the U-
Boot firmware image, which is about 513 KB in size. Both SPI flash contain the same
programming for firmware redundancy and crisis recovery. The SPI flash can be programmed
through the JTAG interface or through an onboard SPI flash programming header.
For information on U-boot and ENV Variables location see, Flash Memory Map, Table 5-2 on
page 96.