Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
77
4.3 System Memory
The P2020 integrated memory controller supports both DDR2 and DDR3 memory devices. It
has one channel and can be configured up to four memory banks with x8, x16 and x32 devices.
Selection of 4GB devices allows support of up to 16 GB of memory. ECC is also supported.
The MVME2502 design implements 2 banks of 9x8 devices which includes ECC. The standard
configurations populate a single memory bank of 2Gb DDR3-800 for a 2GB capacity. The
MVME2502 is designed to accommodate 4Gb DDR3 devices supporting up to 8 Gb total when
both memory banks are populated with 4Gb devices.
4.4 Timers
There are various timer functions implemented on the MVME2502 platform:
For the following options, no strapping options provided. They are only listed for reference.
LGPL1 cfg_sgmii2 No 1 eTSEC2 interface operates in parallel
interface mode (default)
TSEC_1588_ALARM_
OUT2
cfg_sgmii3 No 1 eTSEC3 interface operates in parallel
interface mode (default)
TSEC_1588_ALARM_
OUT1
cfg_srds_refclk No 1 100MHz SERDES ref clock for PCIE
(default)
LWE1/LBS1 LA[18:19] cfg_host_agt[0:2
]
No 111 Processor acts as the host root
complex for all PCIE busses(default)
TSEC2_TXD[4:2] cfg_device_ID[7:
5]
No 111 Rapid IO interface not used => default
values used
LAD[0:15] cfg_gpinput[0:15
]
No No default value. Input pins do not
have internal pull-up resistors
LGPL0 cfg_rio_sys_size No 1 Rapid IO interface not used => default
values used
Table 4-2 P2020 Strapping Options
Functional Signal
Name
Reset
Configuration
Name
Config
Resistor
Options
Default
Value Description