Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
76
LA24 cfg_core0_speed Yes 1 ENP1:
Core0 clock frequency is greater than
1000MHz
0 ENP2:
Core0 clock frequency is less than or
equal to 1000MHz
LA25 cfg_core1_speed Yes 1 ENP1:
Core1 clock frequency is greater than
1000MHz
0 ENP2:
Core1 clock frequency is less than or
equal to 1000MHz
LA26 cfg_ddr_speed Yes 1 DDR Controller complex clock
frequency (same as DDR rate) is
greater than or equal to 500 MHZ
(default)
LVDD_VSEL Yes 1 eTSEC, ethernet management, 1588
interfaces = 2.5V
BVD_VSEL[0:1] Yes 11 Local bus and GPIO[8:15] interfaces =
3.3V
CVDD_VSEL[0:1] Yes 00 USB, eSDHC, SPI interface = 3.3V
LA[20:22]
UART_SOUT[0]
TRIG_OUT
MSRCID[1]
MSRCID[4]
DMA1_DDONE_B[0]
cfg_en_use[0:7] Yes 111111
11
default
TSEC2_TXD1 cfg_dram_type Yes 1 DDR3 SDRAM selected 1.5V (default)
TSEC2_TXD5 cfg_sdhc_cd_pol
_sel
Yes 1 SDHC polarity detect = not inverted
TSEC1_TXD[6:4]
TSEC1_TX_ER
cfg_rom_loc[0:3] Yes 0110 Location of boot ROM = SPI FLASH
Table 4-2 P2020 Strapping Options
Functional Signal
Name
Reset
Configuration
Name
Config
Resistor
Options
Default
Value Description