Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
75
LWE0_N
UART_SOUT1
READY_P1
cfg_core1pii[0:2] Yes 110 ENP1:
3:1 ratio, CCB clock= 400MHz, Core
clock=1200MHz
101 ENP2:
2.5:1 ratio, CCB clock= 400MHz, Core
clock=1000MHz
LA27
LA16
cfg_cup0_boot
cfg_cpu1_boot
Yes 10 CPU0 boot without waiting. CPU1
holdoff
LGPL3/LFW
PLGPL5
cfg_boot_seq[0:1
]
Yes 11 Boot sequencer is disabled. No I2C
ROM is accessed (default)
DMA2_DACK0 cfg_mem_debug Yes 1 DDR SDRAM controller debug info
driven to MSRCID/MDVAL (default)
DMA2_DDONE0 cfg_ddr_debug Yes 1 Debug information is not driven on
ECC pins (default)
EC_MDC cfg_tsec_reduce Yes 0 eTSEC1 and eTSEC2 Ethernet
interfaces operate in RGMII mode
TSEC1_TXD[0,7] cfg_tsec1_prctcl[
0:1]
Yes 10 The eTSEC1 controller operates using
the RGMII protocol
TSEC2_TXD[0,7] cfg_tsec2_prctcl[
0:1]
Yes 10 The eTSEC2 controller operates using
the RGMII protocol
UART_RTS0,UART_R
TS1
cfg_tsec3_prctcl[
0:1]
Yes 10 The eTSEC3 controller operates using
the RGMII protocol
TSEC1_TXD[3:1]
TSEC2_TX_ERR
cfg_io_ports[0:3] Yes 0010 PCIE1=1x, PCIE2=1x, PCI3=2x
MSRCID0 cfg_elbc_ecc Yes 0 eLBC ECC checking is disabled
LA28 cfg_sys_speed Yes 1 SYSCLK is at or above 66MHz
(default)
LA23 cfg_plat_speed Yes 1 Platform clock is at or above 333MHz
(default)
Table 4-2 P2020 Strapping Options
Functional Signal
Name
Reset
Configuration
Name
Config
Resistor
Options
Default
Value Description