Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
74
NOTE: The standard versions of the MVME2502 do not use the encryption enabled versions of
the P2020 processor.
4.2.13 Common On-Chip Processor (COP)
The COP is the debug interface of the QorIQ P2020 Processor. It allows a remote computer
system to access and control the internal operation of the processor. The COP interface
connects primarily through the JTAG and has additional status monitoring signals. The COP has
additional features like breakpoints, watch points, register and memory
examination/modification and other standard debugging features.
4.2.14 P2020 Strapping Pins
The following table lists all the P2020 strapping pins and the default configuration settings for
the MVME2502.
Table 4-2 P2020 Strapping Options
Functional Signal
Name
Reset
Configuration
Name
Config
Resistor
Options
Default
Value Description
LA[29:31] cfg_sys_pii[0:2] Yes 000 4:1 ratio CCB clock: SYSCLK
=100MHz, CCB=400Mhz
TSEC_1588_CLKOUT
TSEC_1588_PULSE_
OUT1
TSEC_1588_PULSE_
OUT2
cfg_ddr_pii[0:2] Yes 011 8:1 ratio, DDRCLK=100MHz, DDRPLL
(data
rate) = 800MHz
LBCTL
LALE
LGPL2/LOE/LFRE
cfg_core0pii[0:2] Yes 110
101
ENP1:
3:1 ratio, CCB clock= 400MHz, Core
clock=1200MHz
ENP2:
2.5:1 ratio, CCB clock= 400MHz, Core
clock=1000MHz