Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
72
4.2.7 USB Interface
The P2020 implements a USB 2.0 compliant serial interface engine. For more information, see
USB, on page 85.
4.2.8 DUART
The chipset provides two universal asynchronous receiver/transmitter (UART). Each UART is
clocked by the CCB clock and is compatible with PC16522D. As a full-duplex interface, it
provides a 16-byte FIFO for both transmitter and receiver mode.
4.2.9 DMA Controller
The DMA controller transfers blocks of data between the various interfaces and functional
blocks of P2020 that are independent of the e500 cores. The P2020 DMA controller has three
high-speed DMA channels, all of which capable of complex data movement and advanced
transaction chaining.
4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)
The eTSEC controller of the device interface to10 Mbps, 100 Mbps, and 1 Gbps Ethernet/IEE
802.3 networks, and devices featuring generic 8 to 16-bit FIFO ports. The MVME2502 uses the
eTSEC using the RGMII interface.
4.2.11 General Purpose I/O (GPIO)
The P2020 has a total of sixteen I/O ports. Four of these ports are used alternately as external
input interrupt. All sixteen ports have open drain capabilities.
The table below details the GPIO usage for the MVME2502:
Table 4-1 P2020 GPIO Functions
GPIO bit CPU Pin # Function
15 E24 Not connected
14 F24 Not connected