Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
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 Double-bit error detection and single-bit error correction ECC, 8-bit check work across 64-
bit data.
 Automatic DRAM initialization sequence or software-controlled initialization sequence
and automatic DRAM data initialization.
 Write leveling for DDR3 memories and supports up to eight posted refreshes.
4.2.3 PCI Express Interface
The PCI Express interface is compatible with the PCI Express Base Specification Rev. 1.0a. The
PCI Express controller connects the internal platform to a 2.5 GHz serial interface. The P2020
has the options for up to three PCIe interfaces with up to x4 link width. The PCIe controller can
be configured to operate as either PCIe root complex (RC) or as an endpoint (EP) device.
4.2.4 Local Bus Controller (LBC)
The main component of the enhanced LBC is the memory controller that provides a 16-bit
interface to various types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by the following: a general purpose
chip select machine (GPCM); a flash controller machine (FCM) and user programmable
machines (UPMs). The MVME2502 supports the GPCM, to interface with the CPLD, MRAM and
QUART.
4.2.5 Secure Digital Host Controller (SDHC)
The ENP1 and ENP2 variants of the MVME2502 use a soldered down 8GB eMMC device
connected to the SDHC interface of the P2020 Processor. This is the only device available on
the SDHC interface.
4.2.6 I
2
C Interface
The MVME2502 has two independent I
2
C buses on the processor. The MVME2502 use port 2
for the XMC modules and I2C port 1 for all other devices. For more information, see I2C Devices,
on page 86.