Technical data

Functional Description
MVME2502 Installation and Use (6806800R96B)
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4.2 Chipset
The MVME2502 utilizes the QorIQ P2020 integrated processor. It offers an excellent
combination of protocol and interface support including dual high performance CPU cores, a
large L2 cache, a DDR2/DDR3 memory controller, three enhanced three-speed Ethernet
controllers, two Serial RapidIO interfaces with a messaging unit, a secure digital interface, a
USB 2.0 interface and three PCI express controllers.
This section describes the protocol and interfaces provided in the QorIQ P2020 integrated and
is utilized by the MVME2502.
4.2.1 e500 Processor Core
The QorIQ integrated processors offer dual high performance e500v2 core (P2020). It operates
from 1.0GHz up to 1.2GHz core frequency. The e500 processor core is a low-power
implementation of the family of reduced instruction set computing (RISC) embedded
processor that implement the Book E definition of the PowerPC architecture. The e500 is a 32-
bit implementation of the Book E architecture using the lower words of 64-bit general-purpose
registers (GPRs) while E500v2 uses 36 bit physical addressing and some improvement from the
previous version.
4.2.2 Integrated Memory Controller
A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and DDR3
memories available. A built-in error checking and correction (ECC) ensures very low bit-error
rates for reliable high-frequency operation. ECC is implemented on MVME2502.
The memory controller supports the following:
 16 GB of memory
 Asynchronous clocking from platform clock, with programmable settings that meets all
the SDRAM timing parameters.
 Up to four physical banks; each bank can be independently addressed to 64 Mbit to 4 Gbit
memory devices (depending on the internal device configuration with x8/x16/x32 data
ports).
 Chip set interleaving and partial array self-refresh.
 Data mask signal and read-modify-write for sub-double-word writes when ECC is enabled.