Technical data

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96B)
109
5.5.15 PLD GPIO2 Interrupt Register
The Abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2502 provides
an interrupt register that the system software reads to determine which device the interrupt
originated from. GPIO2 will be driven "low" if any of the interrupts asserts.
Table 5-18 PLD GPIO2 Interrupt Register
REG PLD Write Protect I2C Debug- 0xFFDF0095
Bit 765432 1 0
Field CPU_RT
C_SEL
SW2-3 RSVD RSVD NMI TICK0_INT TICK1_INT TICK2_INT
OPER R
RESET00X000 0 0
Field Description
CPU_RTC_SEL CPU RTC Input Select
0-1.824MHz (default)
1-SQW/INTB from DS1337 RTC
SW2-3 SW2-3 state (User defined)
0-SW2-3 closed
1-SW2-3 open (default)