Technical data

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96B)
107
5.5.13 PLD Test Register 1
The MVME2502 PLD provides an 8-bit general purpose read/write register which can be used
by the software for PLD testing or general status bit storage.
USER_WP- USER FLASH write-protect
1 - USER I2C FLASH writes disabled
0 - USER I2C FLASH writes enabled
I2C_DEBUG_EN I2C debug ports (I2C_1_D and I2C_1_C) enable
1 - Drive Enabled
0 - Drive Disabled
SERIAL_FLASH_WP SPI devices write-protect register
0 - SPI FLASH writes enabled
1 - SPI FLASH writes disabled
I2C_1_D I2C debug port-Data
0 - Driven Low
1 - HiZ
I2C_1_C I2C debug port-Clock
0 - Driven Low
1 - HiZ
When SERIAL_FLASH_WP is set to "Low", this port will automatically read as low due to "AND"
connection between the two ports.
Table 5-16 PLD Test Register 1
REG PLD Test Register 1- 0xFFDF0008
Bit76543210
Field TEST_REG1
OPER R/W