Technical data

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96B)
103
5.5.9 PLD PCI/PMC/XMC (Slot2) Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the status of the
SATA/PMC/XMC interface signals.
Table 5-12 PLD PCI/PMC/XMC (Slot2) Monitor Register
REG PLD PCI_PMC_XMC_MNTR - 0xFFDF001F
Bit76543210
Field SD1_M
UX_SEL
1
SD1_M
UX_SEL
0
SW2-4 PMC2_E
READY
SATA0_
DETECT
_N
PMC2P_
N
XMCP2_
N
PMC2_P
CIXCAP
OPER R
RESETXXXXXXXX
Field Description
SD1_MUX_SEL[1:0] Select for PCIe MUX1 (Read Only)
11 - XMC (default)
10 - PMC
01-SATA
00-Unused
SW2-4 SW2-4 state (User defined)
0 - SW2-4 closed
1 - SW2-4 open (default)
PMC2_EREADY Indicates PCI device is ready for enumeration.
1 - PMC ready for enumeration
0 - PMC is not ready for enumeration