Technical data

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96B)
102
5.5.8 PLD PCI/PMC/XMC (Slot1) Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the status of the PCI/PMC/XMC
interface signals.
Table 5-11 PLD PCI/PMC/XMC (Slot1) Monitor Register
REG PLD PCI_PMC_XMC_MNTR - 0xFFDF001D
Bit76543210
Field RSVD RSVD MUX1_S
EL_SW
SW2-4 PMC1_E
READY
PMC1P_
N
XMCP1_
N
PCI1_PC
IXCAP
OPER R
RESET001XXXXX
Field Description
MUX1_SEL_SW Select for PCIe MUX1 (R/W)
1 - PMC
0 - XMC
SW2-4 SW2-4 state (User defined)
0 - SW2-4 closed
1 - SW2-4 open (default)
PMC1_EREADY Indicates PCI device is ready for enumeration.
1 - PMC ready for enumeration
0 - PMC is not ready for enumeration
PMC1P_N PMC Presence Indicator
1 - PMC is not present
0 - PMC is present
XMCP1_N XMC Presence Indicator
1 - XMC is not present
0 - XMC is present
PCI1_PCIXCAP PCI Capability Indicator
1 - PCI-X capable
0 - PCI capable