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ManualsBrandsArtesyn ManualsComputer equipmentMVME2502

MVME2502

Installation and Use

P/N: 6806800R96B

April 2014

Summary of content (160 pages)

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MVME2502 Installation and Use P/N: 6806800R96B April 2014
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© Copyright 2014 Artesyn Embedded Technologies, Inc. All rights reserved. Trademarks Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc.© 2014 Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1 1.2 1.3 1.4 1.5 2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 2.2 2.
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Contents Contents 3.5 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1 4.2 4.3 4.4 4 3.4.1.2 Front Panel Serial Port (J4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4.1.3 USB Connector (J5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.4.1.4 VMEBus P1 Connector . . . . . . . . . . . . . .
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Contents 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.4.1 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.2 P2020 Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Contents 5 Memory Maps and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1 5.2 5.3 5.4 5.5 5.6 6 Boot System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.1 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 6.2 6.3 6.4 6.5 6.6 7 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.1 7.2 7.3 7.4 7.5 7.6 7.7 A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Contents B.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 5-1 Table 5-2 Key Features of the MVME2502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 5-21 Table 5-22 Table 5-23 Table 5-24 Table 5-25 Table 5-26 Table 5-27 Table 5-28 Table 5-29 Table 5-30 Table 6-1 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 10 Linux Devices Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table B-1 Table B-2 Table B-3 Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . . 145 Manufacturers’ Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables 12 MVME2502 Installation and Use (6806800R96B)
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List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure A-1 Figure A-2 MVME2502 Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Number Location-ENP1 Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Number Location-ENP2 Variant . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 14 MVME2502 Installation and Use (6806800R96B)
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About this Manual Overview of Contents This manual is divided into the following chapters and appendices.  Introduction gives an overview of the features of the product, standard compliances, mechanical data, and ordering information.  Hardware Preparation and Installation outlines the installation requirements, hardware accessories, switch settings, and installation procedures.  Controls, LEDs, and Connectors describes external interfaces of the board. This includes connectors and LEDs.
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About this Manual About this Manual 16 Term Definition DUART Dual UART EEPROM Erasable Programmable Read-Only Memory FCC Federal Communications Commission GB GigaByte Gbit Gigabit Gbps Gigabits per second HDD Hard Disk Drive I/O Input/Output IEEE Institute of Electrical and Electronics Engineers LED Light Emitting Diode MHz Megahertz MCP Multi-Chip Package MRAM Magnetoresistive Random Access Memory OS Operating System PCB Printed Circuit Board PCI Peripheral Component Inte
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About this Manual Term Definition USB Universal Serial Bus VITA VMEbus International Trade Association VME Versa Module Eurocard XMC PCI Express Mezzanine Card Conventions The following table describes the conventions used throughout this manual.
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About this Manual About this Manual Notation Description | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered. Pay attention to important information Summary of Changes This manual has been revised and replaces all prior editions.
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Chapter 1 Introduction 1.1 Overview The MVME2502 is a VME form-factor single-board based on the Freescale QorlQ P2020 (dualcore) processor. It has a 6U form-factor and has an expansion slot for two PCI Mezzanine Card (PMC) or PCI express Mezzanine Card (XMC). It comes with 2 GB of DDR3 SDRAM, and is offered with either IEEE 1101.10 compliant or SCANBE ejector handles. The front panel I/O configuration consists of two RJ45 10/100/1000BASE-T Ethernet ports, a USB 2.
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Introduction Table 1-1 Key Features of the MVME2502 (continued) Function Features Front panel I/O  Micro DB9 RS-232 serial console port  USB 2.
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Introduction Table 1-1 Key Features of the MVME2502 (continued) 1.2 Function Features Operating System  Based from BSP provided by Freescale which is based from standard Linux version 2.6.32-rc3  Development tool is ltib 9.1.1 (Linux Target Image Builder) from Freescale  VxWorks Standard Compliances The product is designed to meet the following standards. Results are pending until testing is finished.
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Introduction Figure 1-1 MVME2502 Declaration of Conformity EC Declaration of Conformity According to EN 17050-1:2004 Manufacturer’s Name: Artesyn Embedded Technologies Manufacturer’s Address: Zhongshan General Carton Box Factory Co. Ltd.
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Introduction 1.3 Mechanical Data The following table provides details about the dimensions and weight of the board. Table 1-3 Mechanical Data 1.4 Feature Value Height 233.44 mm (9.2 inches) Depth 160.0 mm (6.3 inches) Front Panel Height 261.8 mm (10.3 inches) Width 19.8 mm (0.8 inches) Max. Component Height 14.8 mm (0.58 inches) Weight 400 grams (ENP1), 700 grams (ENP2) Ordering Information As of the printing date of this manual, this guide supports the models listed below.
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Introduction As of the printing date of this manual, the following board accessories are available.
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Introduction 1.5 Product Identification The following graphics shows the location of the serial number label.
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Introduction Figure 1-3 26 Serial Number Location-ENP2 Variant MVME2502 Installation and Use (6806800R96B)
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Chapter 2 Hardware Preparation and Installation 2.1 Overview This chapter provides installation and safety instructions for this product. Installation instructions for the optional PMC and transition module are also included. A fully implemented MVME2502 consists of the base board plus:  PCI Mezzanine Card (PMC) or PCI-E Mezzanine Card (XMC) for added versatility  Rear transition module  SATA kit NOTE: MVME2502-HDMNKIT1/MVME2502-HDMNKIT2 is provided based on purchase order.
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Hardware Preparation and Installation 2.2 Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the product.  Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.  Before touching the board or electronic components, make sure that you are working in an ESD-safe environment. Shipment Inspection 1. Verify that you have received all items of your shipment. 2.
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Hardware Preparation and Installation 2.3.1 Environmental Requirements Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature.
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Hardware Preparation and Installation Product Damage 2.3.2  High humidity and condensation on the board surface causes short circuits.  Do not operate the board outside the specified environmental limits.  Make sure the board is completely dry and there is no moisture on any surface before applying power. Power Requirements The board uses +5.0 V from the VMEbus backplane. On board power supply generates the required voltages for the various ICs.
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Hardware Preparation and Installation The following table shows the power available when the MVME2502 is installed in either a three row or five row chassis and when PMCs are present. Chassis Type Available Power Power With PMCs Three Row 70 W maximum below 70 W Five Row 90 W maximum below 90 W Keep below power limit. Cooling limitations must be considered. 2.3.3 Equipment Requirements The following are recommended to complete a MVME2502 system: 2.
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Hardware Preparation and Installation 2.5 Installing Accessories 2.5.1 Rear Transition Module The MVME2502 does not support hot swap. Remove power to the rear slot or system before installing the module. A PCMI/O Module (PIM) needs to be manually configured and installed before placing the transition module. Damage of Circuits  Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.
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Hardware Preparation and Installation 4. Install the top and bottom edge of the transition module into the rear guides of the chassis. 5. Ensure that the levers of the two injector/ejectors are in the outward position. 6. Slide the transition module into the chassis until resistance is felt. 7. Move the injector/ejector levers in an inward direction. 8. Verify that the transition module is properly seated and secure it to the chassis using the two screws adjacent to the injector/ejector levers. 9.
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Hardware Preparation and Installation 1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis as a ground. Make sure that it is securely fastened throughout the procedure. 2. Remove the PMC/XMC filler plate from the front panel cut-out. 3. Slide the front bezel of the PMC/XMC into the cut-out from behind. The front bezel of the PMC/XMC module will be flushed with the board when the connectors on the module align with the mating connectors on the board. 4.
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Hardware Preparation and Installation 2.5.3 Installation of MVME2502-HDMNTKIT1/MVME2502HDMNTKIT2 Installation Procedure 1. Attach washers and hex standoffs to HDD received with the MVME2502-HDMNTKIT1 / MVME2502-HDMNTKIT2. 2. Mate the SATA adapter board to the blade, making sure that it is properly aligned with the standoff. Use the screws to anchor the SATA adapter board to the blade.
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Hardware Preparation and Installation 3. Attach hex standoff to main board.
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Hardware Preparation and Installation 4. Attach HDD with interface PCB to main board using screws as shown below: 2.6 Installing and Removing the Board This section describes the recommended procedure for installing the board in a chassis. Read all warnings and instructions before installing the board. The MVME2502 does not support hot swap. Power off the slot or system and make sure that the serial ports and switches are properly configured.
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Hardware Preparation and Installation Damage of Circuits  Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.  Before touching the board or electronic components, make sure that you are working in an ESD-safe environment. Product Damage  Only use injector handles for board insertion to avoid damage to the front panel and/or PCB. Deformation of the front panel can cause an electrical short or other board malfunction. 1.
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Hardware Preparation and Installation 2.7 Completing the Installation The board is designed to operate as an application-specific computer blade or an intelligent I/O board/carrier. It can be used in any slot in a VME chassis. Once the board is installed, you are ready to connect peripherals and apply power to the board. Product Damage  RJ-45 connectors on modules are either twisted-pair Ethernet (TPE) or E1/T1/J1 network interfaces.
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Hardware Preparation and Installation 40 MVME2502 Installation and Use (6806800R96B)
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Chapter 3 Controls, LEDs, and Connectors 3.1 Board Layout The following figure shows the components and connectors on the MVME2502.
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Controls, LEDs, and Connectors Figure 3-2 42 Board Layout ENP2 Variant MVME2502 Installation and Use (6806800R96B)
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Controls, LEDs, and Connectors 3.2 Front Panel The following components are found on the MVME2502 ENP1 and ENP2 front panel.
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Controls, LEDs, and Connectors 3.2.1 Reset Switch The MVME2502 has a single push button switch that has both the abort and reset functions. Pressing the switch for less than three seconds can generate an abort interrupt if there is firmware that will read the GPIO2 (0xffdf0095) interrupt register. U-boot does not implement any interrupts and also does not detect the interrupt or display anything when the button is pressed. Holding it down for more than three seconds will generate a hard reset.
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Controls, LEDs, and Connectors Table 3-1 Front Panel LEDs (continued) Label Function Location Color Description FAIL Board Fail Front panel Off Normal operation after successful firmware boot. Red One or more on-board power rails has failed and the board has shutdown to protect the hardware. Normal during power up, during hardware reset (such as a front panel reset). May be asserted by the BDFAIL bit in the Tsi148 VSTAT register.
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Controls, LEDs, and Connectors 3.3.2 Onboard LEDs The onboard LEDs are listed below. The LEDs are located on the rear side of the board just opposite of the battery location. To view the board, see Figure 3-1 on page 41. Figure 3-5 Onboard LEDs Table 3-2 Onboard LEDs Status 46 Label Function Color Description D9 Power Fail Red This indicator is illuminated when one or more of the onboard voltage rails fails. D33 User Defined Amber Controlled by the CPLD. Used for boot-up sequence indicator.
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Controls, LEDs, and Connectors 3.4 Connectors This section describes the pin assignments and signals for the connectors on the MVME2502. 3.4.1 Front Panel Connectors The following connectors are found on the outside of the MVME2502. These connectors are divided between the front panel connectors and the backplane connectors. The front panel connectors include the J1 and J5 connectors. The backplane connectors include the P1 and P2 connectors. 3.4.1.
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Controls, LEDs, and Connectors Table 3-3 Front Panel Tri-Speed Ethernet Connector (J1) (continued) 3.4.1.
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Controls, LEDs, and Connectors Table 3-4 Front Panel Serial Port (J4) 3.4.1.3 Pin Signal Description 7 RTS 8 CTS 9 NC USB Connector (J5) The MVME2502 uses upright USB receptacle mounted in the front panel. Table 3-5 USB Connector (J5) 3.4.1.4 Pin Name Signal Description 1 +5 V 2 Data - 3 Data + 4 GND MTG Mounting Ground MTG Mounting Ground MTG Mounting Ground MTG Mounting Ground VMEBus P1 Connector The VME P1 connector is a 160-pin DIN.
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Controls, LEDs, and Connectors Table 3-6 VMEbus P1 Connector (continued) 50 Pin Row A Row B Row C Row D Row Z 4 DATA 3 BGIN0 DATA 11 NC GND 5 DATA 4 BGOUT0 DATA 12 NC NC 6 DATA 5 BGIN1 DATA 13 NC GND 7 DATA 6 BGOUT1 DATA 14 NC NC 8 DATA 7 BGIN2 DATA 15 NC GND 9 GND BGOUT2 GND GAP NC 10 SYSCLK BGIN3 SYSFAIL GA0 GND 11 GND BGOUT3 BERR GA1 NC 12 DS1 BR0 SYSRESET +3.3V (not used) GND 13 DS0 BR1 LWORD GA2 NC 14 WRITE BR2 AM 5 +3.
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Controls, LEDs, and Connectors Table 3-6 VMEbus P1 Connector (continued) 3.4.1.5 Pin Row A Row B Row C Row D Row Z 31 -12V NC +12V +12V NC 32 +5V +5V +5V +5V GND VMEBus P2 Connector The VME P2 connector is a 160-pin DIN. Row B of the P2 connector provides power to the MVME2502 and to the upper eight VMEbus address lines and additional 16 VMEbus data lines.
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Controls, LEDs, and Connectors Table 3-7 VMEbus P2 Connector (continued) Pin Row A Row B Row C Row D Row Z 18 PMC IO 36 DATA 20 PMC IO 35 GE4_A_LED GND 19 PMC IO 38 DATA 21 PMC IO 37 GND Serial 3 TX 20 PMC IO 40 DATA 22 PMC IO 39 GE4_3 - GND 21 PMC IO 42 DATA 23 PMC IO 41 GE4_3 + Serial 3 CTS 22 PMC IO 44 GND PMC IO 43 GND GND 23 PMC IO 46 DATA 24 PMC IO 45 GE4_2 - Serial 3 RTS 24 PMC IO 48 DATA 25 PMC IO 47 GE4_2+ GND 25 PMC IO 50 DATA 26 PMC IO 49 GND
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Controls, LEDs, and Connectors Table 3-8 Custom SATA Connector (J3) (continued) 3.4.2.2 Pin Signal Description Pin Signal Description 4 SATA TX + 24 SATA DETECT 5 NC 25 NC 6 SATA TX - 26 GND 7 GND 27 NC 8 GND 28 GND 9 GND 29 GND 10 GND 30 GND 11 NC 31 +3.3V 12 SATA RX - 32 +5V 13 NC 33 +3.3V 14 SATA RX + 34 +5V 15 GND 35 +3.3V 16 GND 36 +5V 17 NC 37 +3.3V 18 GND 38 +5V 19 NC 39 +3.
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Controls, LEDs, and Connectors Table 3-9 PMC J11/J111 Connector (continued) 54 Pin Signal Description Pin Signal Description 3 GND 35 GND 4 INT A 36 IRDY 5 INT B 37 DEVSEL 6 INT C 38 +5V 7 PRESENT SIGNAL 39 PCIXCAP 8 +5V 40 LOCK 9 INT D 41 NC 10 NC 42 NC 11 GND 43 PAR 12 NC 44 GND 13 PCI CLK 45 +3.3V 14 GND 46 AD 15 15 GND 47 AD 12 16 GNT A 48 AD 11 17 REQ A 49 AD 9 18 +5V 50 +5V 19 +3.
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Controls, LEDs, and Connectors Table 3-9 PMC J11/J111 Connector (continued) Pin Signal Description Pin Signal Description 30 +5V 62 +5V 31 +3.3V 63 GND 32 AD 17 64 REQ64 Table 3-10 PMC J12/J222 Connector Pin Signal Description Pin Signal Description 1 +12V 33 GND 2 JTAG TRST 34 IDSELB 3 JTAG TMS 35 TRDY 4 JTAG TDO 36 +3.3V 5 JTAG TDI 37 GND 6 GND 38 STOP 7 GND 39 PERR 8 NC 40 GND 9 NC 41 +3.
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Controls, LEDs, and Connectors Table 3-10 PMC J12/J222 Connector (continued) Pin Signal Description Pin Signal Description 22 AD 26 54 GNTB 23 AD 24 55 NC 24 +3.3V 56 GND 25 IDSEL 57 NC 26 AD 23 58 EREADY 27 +3.3V 59 GND 28 AD 28 60 RSTOUT 29 AD 18 61 ACK64 30 GND 62 +3.
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Controls, LEDs, and Connectors Table 3-11 PMC J13/J333 Connector (continued) Pin Signal Description Pin Signal Description 14 GND 46 AD 40 15 GND 47 AD 39 16 AD 60 48 AD 38 17 AD 59 49 AD 37 18 AD 58 50 GND 19 AD 57 51 GND 20 GND 52 AD 36 21 +3.3V 53 AD 35 22 AD 56 54 AD 34 23 AD 55 55 AD 33 24 AD 54 56 GND 25 AD 53 57 +3.
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Controls, LEDs, and Connectors Table 3-12 PMC J14 Connector (continued) 58 Pin Signal Description Pin Signal Description 6 PMC IO 6 38 PMC IO 38 7 PMC IO 7 39 PMC IO 39 8 PMC IO 8 40 PMC IO 40 9 PMC IO 9 41 PMC IO 41 10 PMC IO 10 42 PMC IO 42 11 PMC IO 11 43 PMC IO 43 12 PMC IO 12 44 PMC IO 44 13 PMC IO 13 45 PMC IO 45 14 PMC IO 14 46 PMC IO 46 15 PMC IO 15 47 PMC IO 47 16 PMC IO 16 48 PMC IO 48 17 PMC IO 17 49 PMC IO 49 18 PMC IO 18 50 PMC IO 50 19
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Controls, LEDs, and Connectors 3.4.2.3 JTAG Connector (P6) The JTAG Connector can be used in conjunction with the JTAG board and ASSET hardware. Table 3-13 JTAG Connector (P6) Pin Signal Description Pin Signal Description 1 NC 2 +3.3V FROM +5V 3 SPI HOLD 0 4 SPI CS 0 5 SPI CLK 6 SPI CS 1 7 SPI HOLD 1 8 SPI MOSI 9 SPI MISO 10 GND 11 SPI VCC 12 SCAN 1 TCK 13 SCAN 1 TDI 14 GND 15 SCAN 1 TRST 16 SCAN 1 TDO 17 SCAN 1 TMS 18 +3.
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Controls, LEDs, and Connectors Table 3-13 JTAG Connector (P6) (continued) 3.4.2.4 Pin Signal Description Pin Signal Description 49 SCAN 4 TCK 3 50 SCAN 4 TRST 51 SCAN 5 TMS 52 SCAN 5 53 SCAN 5 TDO 54 GND 55 +3.3V 56 SCAN5 TCK2 57 SCAN 5 TDI 58 GND 59 SCAN 5 TRST 60 NC COP Connector (P6) The COP header is used for the CPU debug. The pin assignment is dictated by Freescale and is compatible with the processor’s debugging tool.
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Controls, LEDs, and Connectors Table 3-14 COP Header (P10) 3.4.2.5 Pin Signal Description 15 COP CHECK STOP OUT 16 GND XMC Connector (XJ1) The MVME2502 supports two XMC sites. The board only support J15 for XMC site 1 and J25 for XMC site 2. Table 3-15 XMC Connector (XJ1) Pin out Pin Row A Row B Row C Row D Row E Row F 1 RX0 + RX0 - +3.3V NC NC +3.3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC +3.3V NC NC +3.
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Controls, LEDs, and Connectors Table 3-15 XMC Connector (XJ1) Pin out (continued) Pin Row A Row B Row C Row D Row E Row F 17 NC NC NC NC NC NC 18 GND GND NC GND GND NC 19 CLK + CLK - NC ROOT 0 ROOT0 (PULLED UP) NC (PULLED UP) 3.4.2.6 XMC Connector (XJ2) Table 3-16 XMC Connector (XJ2) Pin out Pin Row A Row B Row C Row D Row E Row F 1 RX0 + RX0 - +3.3V RX1+ RX1- +3.3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC +3.3V NC NC +3.
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Controls, LEDs, and Connectors Table 3-16 XMC Connector (XJ2) Pin out (continued) Pin Row A Row B Row C Row D Row E Row F 16 GND GND MVMRO (PULLED DOWN) GND GND I2C CLOCK 17 NC NC NC NC NC NC 18 GND GND NC GND GND NC 19 CLK + CLK - NC NC ROOT0 (PULLED UP) NC 3.4.2.
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Controls, LEDs, and Connectors 3.5 Switches These switches control the configuration of the MVME2502. Board Malfunction 3.5.1  Switches marked as “reserved” might carry production-related functions and can cause the board to malfunction if their settings are changed.  Do not change settings of switches marked as “reserved”. The setting of switches which are not marked as “reserved” has to be checked and changed before board installation.
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Controls, LEDs, and Connectors Note that this switch is wired in parallel with the geographical address pins on the five row connector. These switches must be in the "OFF" position when installed in a five row chassis in order to get the correct address from the P1 connector. This switch also includes the SCON control switches.
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Controls, LEDs, and Connectors 3.5.2 SMT Configuration Switch (S2) This eight position SMT configuration switch controls the flash bank user defined switch, selects the flash boot image, and controls the safe start ENV settings. The default setting on all switch positions is "OFF" and is indicated by brackets in Table 3-19.
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Controls, LEDs, and Connectors Table 3-19 Geographical Address Switch Settings (continued) SW2 DEFAULT Signal Name Description Notes 6 OFF (WP Enabled) MASTER_WP_DISA BLED EEPROM Write-Protect For I2C write-protect only. 7 OFF (Front) GBE_MUX_SEL User Defined switch that will select if the GBE PHY will function on the front panel or on the Back PLANE 8 OFF (CPU Reset Deasserted) Reserved MVME2502 Installation and Use (6806800R96B) Should be "OFF" for normal operation.
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Controls, LEDs, and Connectors 68 MVME2502 Installation and Use (6806800R96B)
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Chapter 4 Functional Description 4.1 Block Diagram The MVME2502 block diagram is illustrated in Figure 4-1. All variants provide front panel access to one serial port via a micro-mini DB-9 connector, two 10/100/1000 Ethernet port (one is configurable to be routed on the front panel or to the rear panel) through a ganged RJ45 connector and one Type A USB Port. It includes Board Fail LED indicator, user-defined LED indicator and a ABORT/RESET switch.
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Functional Description 4.2 Chipset The MVME2502 utilizes the QorIQ P2020 integrated processor. It offers an excellent combination of protocol and interface support including dual high performance CPU cores, a large L2 cache, a DDR2/DDR3 memory controller, three enhanced three-speed Ethernet controllers, two Serial RapidIO interfaces with a messaging unit, a secure digital interface, a USB 2.0 interface and three PCI express controllers.
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Functional Description 4.2.3  Double-bit error detection and single-bit error correction ECC, 8-bit check work across 64bit data.  Automatic DRAM initialization sequence or software-controlled initialization sequence and automatic DRAM data initialization.  Write leveling for DDR3 memories and supports up to eight posted refreshes. PCI Express Interface The PCI Express interface is compatible with the PCI Express Base Specification Rev. 1.0a.
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Functional Description 4.2.7 USB Interface The P2020 implements a USB 2.0 compliant serial interface engine. For more information, see USB, on page 85. 4.2.8 DUART The chipset provides two universal asynchronous receiver/transmitter (UART). Each UART is clocked by the CCB clock and is compatible with PC16522D. As a full-duplex interface, it provides a 16-byte FIFO for both transmitter and receiver mode. 4.2.
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Functional Description Table 4-1 P2020 GPIO Functions GPIO bit CPU Pin # Function 13 E23 Connected to pin R7 of the CPLD (unused input) 12 F23 Connected to pin M8 of the CPLD (unused input) 11 D24 Connected to pin M7 of the CPLD (unused input) 10 A25 Not connected 09 A24 Not connected 08 F22 Not connected 07 R25 Not connected 06 R29 Connected to pin T6 of the CPLD (unused input) 05 R24 Connected to pin R6 of the CPLD (unused input) 04 U29 Connected to INTA of the QUART.
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Functional Description NOTE: The standard versions of the MVME2502 do not use the encryption enabled versions of the P2020 processor. 4.2.13 Common On-Chip Processor (COP) The COP is the debug interface of the QorIQ P2020 Processor. It allows a remote computer system to access and control the internal operation of the processor. The COP interface connects primarily through the JTAG and has additional status monitoring signals.
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Functional Description Table 4-2 P2020 Strapping Options Functional Signal Name Reset Configuration Name Config Resistor Options Default Value LWE0_N cfg_core1pii[0:2] Yes 110 UART_SOUT1 Description ENP1: 3:1 ratio, CCB clock= 400MHz, Core clock=1200MHz READY_P1 101 ENP2: 2.5:1 ratio, CCB clock= 400MHz, Core clock=1000MHz LA27 cfg_cup0_boot LA16 cfg_cpu1_boot Yes 10 CPU0 boot without waiting. CPU1 holdoff LGPL3/LFW Yes 11 PLGPL5 cfg_boot_seq[0:1 ] Boot sequencer is disabled.
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Functional Description Table 4-2 P2020 Strapping Options Functional Signal Name Reset Configuration Name Config Resistor Options Default Value Description LA24 cfg_core0_speed Yes 1 ENP1: Core0 clock frequency is greater than 1000MHz 0 ENP2: Core0 clock frequency is less than or equal to 1000MHz LA25 cfg_core1_speed Yes 1 ENP1: Core1 clock frequency is greater than 1000MHz 0 ENP2: Core1 clock frequency is less than or equal to 1000MHz LA26 cfg_ddr_speed Yes 1 DDR Controller complex c
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Functional Description Table 4-2 P2020 Strapping Options Functional Signal Name Reset Configuration Name Config Resistor Options Default Value Description For the following options, no strapping options provided. They are only listed for reference.
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Functional Description 4.4.1 Real Time Clock The MVME-2502 implements a Maxim DS1337 RTC to maintain seconds, minutes, hours, day, date, month, year accurately. The INT_A pin of the DS1337 is connected to the CPU GPIO[1] pin to allow the DS1337 to generate interrupts to the CPU. Access to the DS1337 is provided via the I2C port 0 from the CPU and responds to a base I2C address of $D0. The MVME2502 provides a socketed 48mAh primary battery to power the RTC when the module is out of service. 4.4.
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Functional Description MVME2502 provides two 10/100/1000 Ethernet interfaces on the front panel and another two are routed to the RTM through the backplane connector. Due to controller limitations, one controller is designed to be routed to the front panel or to the RTM. This setting is possible by using a third party gigabit Ethernet LAN switch with a single enable switch such as PERICOM’s P13L301D. The routing direction can be configured through the on-board dip switch.
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Functional Description 4.6.2 SPI Flash Programming The MVME2502 has three headers: a 10-pin header for SPI Flash programming, an 80-pin header for the JTAG connectivity and a 20-pin JTAG header for ASSET hardware connectivity. The following options are used to program the onboard flash:  Using onboard SPI header - The MVME2502 uses the 10-pin header with a Dual SPI Flash incircuit programming configuration. The pin connection is compatible with DediProg SPI Universal Pin Header.
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Functional Description The MVME2502 CPLD controls the chip select to SPI devices A and B. The CPLD chip select control is based on the Switch Bank (S2-2). Figure 4-2 SPI Device Multiplexing Logic At power-up, the selection of the SPI boot device is strictly based upon the Switch Bank (S2-2) setting. Depending on the S2-2 setting, SPI_SEL0 is routed to one of two SPI devices. The selected SPI device must contain a boot image.
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Functional Description The MVME2502 supports automatic switch over. If booting one device is not successful, the watchdog will trigger the board reset and it will automatically boot on the other device. 4.6.4 Crisis Recovery The MVME2502 provides an independent boot firmware recovery mechanism for the operating system. The firmware recovery can be performed without leaving the firmware environment.
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Functional Description Only 115200 bps and 9600 bps are supported. The default baud rate on the front panel serial is 9600 kbps. 4.8 Rear UART Control The MVME2502 utilizes the Exar ST16C554 quad UART (QUART) to provide four asynchronous serial interface’ to the RTM. These devices feature 16 bytes of transmit and receive first-in firstout (FIFO) with selectable receive FIFO trigger levels and data rates of up to 1.5 Mbps.
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Functional Description PMC/XMC sites are keyed for 3.3V PMC signaling. PMC and XMC add-on cards must have a hole in the 3.3 V PMC keying position in order to be populated on the MVME2502. The XMC specification accommodates this since it is expected that carrier cards will host both XMC and PMC capable add-on cards. The MVME2502 have a keying pin at the 3.3V location at each PMC site. The MVME2502 boards are not 5 volt PMC IO compatible. The MVME2502 also has a 5 volt keying pin location at each PMC site.
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Functional Description 4.10 SATA Interface The MVME2502 supports an optional 2.5" SATA HDD. The connector interface is compatible with the SATAMNKIT, which contains the following: one SSD/HDD, one SATA board, screws and a mounting guide. The SATA connector can support a horizontal mounted SSD/HDD. The MVME2502 uses Marvell's 88SE9125 SATA controller and supports up to 1.5 Gbps, 3.0 Gbps, or 6.0 Gbps (SATA Gen 1).
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Functional Description 4.13 I2C Devices The MVME2502 utilizes two I2C ports provided by the board's processor. The I2C bus is a twowire, serial data (SDA) and serial clock (SCL), synchronous, multi-master bi-directional serial bus that allows data exchange between this device and other devices such as VPD, SPD, EEPROM, RTC, temperature sensor, RTM, XMC and IDT clocking. The user can configure the RTM I2C adders and should be aware to avoid address duplication.
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Functional Description 4.14 Reset/Control CPLD The CPLD provides the following functions: 4.15  Power control and fault detection  Reset sequence and reset management  Status and control registers  Miscellaneous control logic  Watchdog timer  32-bit Tick Timer  Clock generator  Switch decoder and LED controller Power Management The MVME2502 backplane is utilized to derive +3.3V, +2.5V, +1.8V, +1.5V, +1.2V, +1.05V voltage rail.
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Functional Description Table 4-5 Voltage Supply Requirement Voltage Rail Requirement Voltage Rail Minimum Maximum +1.5 V 1.425 V 1.575 V +1.2 V 1.14 V 1.26 V +1.2 V_SW 1.14 V 1.26 V +1.05 V 1.0 V 1.1 V 4.15.2 Power Up Sequencing Requirements The power up sequence describes the voltage rail power up timing, which is designed to support all the chip supply voltage sequencing requirement.
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Functional Description 4.16 Clock Structure A total of three IDT chips, a discrete oscillator and crystal to support all the clock requirements of MVME2502. Figure 4-3 4.17 Clock Distribution Diagram Reset Structure MVME2502 reset will initiate after the power up sequence if the 1.5 V power supply is "GOOD". When the board is at “ready” state, the reset logic will monitor the reset sources and implement the necessary reset function.
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Functional Description 4.17.1 Reset Sequence The timing of the reset sequence supports each chip reset requirements with respect to the power supply. 4.18 Thermal Management The MVME2502 utilizes two on-board temperature sensors: one for the board and the other for the CPU temperature sensor. The board temperature sensor is located near the processor. The CPU temperature sensor is located on the processor.
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Functional Description 4.20.1 POST Code Indicator The following table shows the LED status of the POST Codes. For the location of the POST Code LEDs, see Onboard LEDs, on page 46. Logic 1 means LED is "ON", Logic 2 means LED is "OFF" Table 4-7 POST Code Indicator on the LED Sequence D33 D32 D35 Description 1 Off Off Off U-boot has been copied from SPI flash to CPU cache. 2 Off On Off Serial console has been initialized, some text is visible on the terminal.
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Functional Description The JTAG board provides three different connectors for the ASSET hardware, flash programming and the MVME2502 JTAG connector. The board is equipped with TTL buffers to help improve the signal quality as it traverses over the wires. Figure 4-4 JTAG Chain Diagram 4.20.3 Custom Debugging Custom debugging makes use of the common on-chip processor. Refer to Common On-Chip Processor (COP), on page 74 for details.
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Functional Description 4.21 Rear Transition Module (RTM) The MVME2502 RTM Block diagram is illustrated below: Figure 4-5 RTM Block Diagram The MVME2502 is compatible with the MVME7216E RTM. The MVME7216E RTM is for I/O routing through the rear of a compact VMEbus chassis. It connects directly to the VME backplane in chassis with an 80 mm deep rear transition area.
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Functional Description 94 MVME2502 Installation and Use (6806800R96B)
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Chapter 5 Memory Maps and Registers 5.1 Overview System resources including system control and status registers, external timers, and the QUART are mapped into 16 MB address range accessible from the MVME2502 local bus through the P2020 QorIQ LBC. 5.2 Memory Map The following table shows the physical address map of the MVME2502.
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Memory Maps and Registers 5.3 Flash Memory Map The table below lists the memory range designated to U-boot and ENV variables. Table 5-2 Flash Memory Map 5.4 Description Memory Area U-boot 0x00000000 0x0008ffff Reserved 0x00090000 0x0009ffff ENV Variables 0x00100000 0x0011ffff Available Flash 0x00120000 0x007fffff Linux Devices Memory Map The table below lists the memory ranges designated to different devices in Linux.
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Memory Maps and Registers Table 5-3 Linux Devices Memory Map Device Memory Range Memory Area Size CPLD 0xffdf0000 0xffdf0fff 4 KB ecm local access window CCSR 0xffe00000 0xffe00ffff 4 KB ecm (Error Correction Module) CCSR 0xffe01000 0xffe01fff 4 KB Memory Controller CCSR 0xffe02000 0xffe02fff 4 KB I2C1 CCSR 0xffe03000 0xffe030ff 256 B I2C2 CCSR 0xffe03100 0xffe031ff 256 B UART0 CCSR 0xffe04500 0xffe045ff 256 B UART1CCSR 0xffe04600 0xffe046ff 256 B ELBC CCSR 0xffe05000 0xffe05fff
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Memory Maps and Registers 5.5 Programmable Logic Device (PLD) Registers 5.5.1 PLD Revision Register The MVME2502 provides a PLD revision register that can be read by the system software to determine the current version of the timers/registers PLD. Table 5-4 PLD Revision Register REG PLD Revision Register - 0xFFDF0000 Bit 7 Field PLD Rev OPER R RESET (TBD) 6 5 4 3 2 1 0 Field Description PLD_REV 5.5.2 8-bit field containing the current timer/register PLD revision.
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Memory Maps and Registers 5.5.3 PLD Month Register The MVME2502 PLD provides an 8-bit register which contains the build month of the timers/registers PLD. Table 5-6 PLD Month Register 5.5.4 REG PLD Year Register - 0xFFDF0005 Bit 7 Field PLD Rev OPER R RESET (TBD) 6 5 4 3 2 1 0 PLD Day Register MVME2502 PLD provides an 8-bit register which contains the build day of the timers/registers PLD. Table 5-7 PLD Day Register 5.5.
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Memory Maps and Registers Table 5-8 PLD Sequence Register 5.5.6 REG PLD Revision Register - 0xFFDF0007 Bit 7 Field PLD Rev OPER R RESET (TBD) 6 5 4 3 2 1 0 PLD Power Good Monitor Register The MVME2502 PLD provides an 8-bit register which indicates the instantaneous status of the supply’s power good signals.
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Memory Maps and Registers 5.5.7 PWR_V3P3_PWRGD 3.3V Supply power good indicator PWR_V2P5_PWRGD 2.5V Supply power good indicator PWR_V1P2_SW_PWRG D 1.2V SW Supply power good indicator PWR_V1P5_PWRGD 1.5V Supply power good indicator 1 - Supply Good and Stable 0 - Otherwise PLD LED Control Register The MVME2502 PLD provides an 8-bit register which controls the eight LEDs.
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Memory Maps and Registers 5.5.8 PLD PCI/PMC/XMC (Slot1) Monitor Register The MVME2502 PLD provides an 8-bit register which indicates the status of the PCI/PMC/XMC interface signals.
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Memory Maps and Registers 5.5.9 PLD PCI/PMC/XMC (Slot2) Monitor Register The MVME2502 PLD provides an 8-bit register which indicates the status of the SATA/PMC/XMC interface signals.
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Memory Maps and Registers SATA0_DETECT_N SATA drive presence indicator 1-SATA not present 0-SATA present PMC2P_N PMC Presence Indicator 1 - PMC is not present 0 - PMC is present XMCP2_N XMC Presence Indicator 1 - XMC is not present 0 - XMC is present PMC2_PCIXCAP PCI Capability Indicator 1 - PCI-X capable 0 - PCI capable 5.5.
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Memory Maps and Registers Field Description BDFAIL_N TSI148 BDFAIL_N Pin out 1 - No TSI Fail 0 - TSI Fail NORMAL_ENV Normal Environment Switch Indicator 1 - Use safe ENV 0 - Use normal ENV SCON System Controller Indicator 1 - System Controller 0 - Non-system Controller 5.5.11 PLD Boot Bank Register The MVME2502 PLD provides an 8-bit register which is used to declare successful U-Boot loading, indicating the SPI boot bank priority and actual SPI bank it booted from.
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Memory Maps and Registers Field Description BOOT_BLOCK_A Boot Block Manual Selector Switch 1 - SPI0 0 - SPI1 BOOT_SPI Actual Boot Bank 1 - SP1 0 - SPI0 5.5.12 PLD Write Protect and I2C Debug Register The MVME2502 PLD provides an 8-bit register which is used to indicate the status of I2C and SPI write-protect manual switches and is used to control the SPI write-enable. I2C debug ports are also provided in this register which can be used in controlling the bus’ status.
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Memory Maps and Registers USER_WP- USER FLASH write-protect 1 - USER I2C FLASH writes disabled 0 - USER I2C FLASH writes enabled I2C_DEBUG_EN I2C debug ports (I2C_1_D and I2C_1_C) enable 1 - Drive Enabled 0 - Drive Disabled SERIAL_FLASH_WP SPI devices write-protect register 0 - SPI FLASH writes enabled 1 - SPI FLASH writes disabled I2C_1_D I2C debug port-Data 0 - Driven Low 1 - HiZ I2C_1_C I2C debug port-Clock 0 - Driven Low 1 - HiZ When SERIAL_FLASH_WP is set to "Low", this port will automaticall
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Memory Maps and Registers Table 5-16 PLD Test Register 1 REG PLD Test Register 1- 0xFFDF0008 RESET 00 Field Description TEST_REG1 General purpose 8-bit R/W field 5.5.14 PLD Test Register 2 The MVME2502 PLD provides an 8-bit general purpose read/write register which can be used by the software for PLD testing or general status bit storage.
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Memory Maps and Registers 5.5.15 PLD GPIO2 Interrupt Register The Abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2502 provides an interrupt register that the system software reads to determine which device the interrupt originated from. GPIO2 will be driven "low" if any of the interrupts asserts.
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Memory Maps and Registers NMI Abort switch interrupt if pressed less than three seconds. 1 - Interrupt enabled 0 - No Interrupt TICK0_INT Tick Timer 0 interrupt 1 - Interrupt enabled 0 - No Interrupt TICK1_INT Tick Timer 1 interrupt 1 - Interrupt enabled 0 - No Interrupt TICK2_INT Tick Timer 2 interrupt 1 - Interrupt enabled 0 - No Interrupt 5.5.16 PLD Shutdown and Reset Control and Reset Reason Register The MVME2502 provides an 8-bit register to execute the shutdown and reset commands.
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Memory Maps and Registers Field Description Shutdown Board Shutdown Register 1 - Shutdown Enable 0 - Shutdown Disable Note: If a board entered the shutdown state (by writing a '1' in this register), the chassis' power needs to be cycled to power up the board again.
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Memory Maps and Registers 5.5.17 EMMC Reset Register The MVME2502 provides a register for EMMC Reset. Table 5-20 PLD Shutdown and Reset Control and Reset Reason Register REG EMMC Reset Register Bit 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD EMMC_R ST_N OPER RESET R 0 0 0 0 R/W X X X X Field Description EMMC_RST_N EMMC Reset Bit 1 - Reset is deasserted 0 - Reset is asserted (write 0 to reset EMMC) 5.5.
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Memory Maps and Registers 5.5.19 PLD Watchdog Control Register The MVME2502 provides a watchdog control register. Table 5-22 PLD Watchdog Control Register REG PLD Watch Dog Timer Load - 0xFFC80604 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Watchdog_EN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R/W R RESET 0000 Field Description EN Enable. If cleared, the watchdog timer is disabled. If set, the watchdog timer is enabled. 5.
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Memory Maps and Registers Field Description Count Count. These bits define the watchdog timer count value. When the watchdog counter is enabled, it will count up from zero (reset value) with a 1 ms resolution until it reaches the COUNT value set by this register. Watchdog will generate a soft reset signal if it bites. Setting this register to 0xEA60 or 60,000 counts will provide a watchdog timeout of 60 seconds. 5.5.
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Memory Maps and Registers Prescaler Adjust = 256-(CLKIN/CLKOUT) CLKIN is the input clock source in MHz, and CLKOUT is the desired output clock reference in MHz. Table 5-25 Prescaler Register REG Prescaler Register - 0xFFC80100 Bit 15 14 13 12 11 10 9 8 7 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Prescaler Register (8-bits) OPER R/W RESET 0x00e7 6 5 4 3 2 1 0 The prescaler provides the clock required by each of the three times.
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Memory Maps and Registers Field Description 5.6.3 ENC Enable counter. When the bit is set, the counter increments. When the bit is cleared, the counter does not increment. COC Clear Counter on Compare. When the bit is set, the counter is reset to 0 when it compares with the compare register. When the bit is cleared the counter is not reset. COVF Clear Overflow Bits. The overflow counter is cleared when a 1 is written to this bit. OVF Overflow Bits are the output of the overflow counter.
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Memory Maps and Registers Since the processor is 16-bits and the tick timer is 32-bits, the compare register was split in half. Accessing the whole register will require two transactions.
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Memory Maps and Registers Table 5-29 Counter High Word Registers (continued) Tick Timer 0 Counter Value High Word - 0xFFC80208 Tick Timer 1 Counter Value High Word - 0xFFC80308 REG Tick Timer 2 Counter Value High Word - 0xFFC80408 Field TickTimer Counter Value High Word (16-bits) OPER R/W RESET 0x0000 Table 5-30 Counter Low Word Registers Tick Timer 0 Counter Value Low Word - 0xFFC8020A Tick Timer 1 Counter Value Low Word - 0xFFC8030A REG Tick Timer 2 Counter Value Low Word - 0xFFC8040A Bit 15
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Chapter 6 Boot System 6.1 Overview The MVME2502 uses Das U-Boot, a boot loader software based on the GNU Public License. It boots the blade and is the first software to be executed after the system is powered on. Its main functions are:  Initialize the hardware  Pass boot parameters to the Linux kernel  Start the Linux kernel  Update Linux kernel and U-Boot images This section describes U-Boot features and procedures that are specific to the MVME2502.
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Boot System U-Boot aborts the boot sequence and enters into a command line interface mode. Enter the command setenv bootdelay -1; saveenv to disable the U-Boot auto-boot feature and let the U-Boot directly enter the command line interface after the next reboot/power up. 6.3 Boot Options 6.3.1 Booting from a Network In this mode, U-Boot downloads and boots the Linux kernel from an external TFTP server and mounts a root file system located on a network server. 1.
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Boot System 6.3.2 Booting from an Optional SATA Drive 1. Make sure that the kernel, dtb, and ramdisk are saved in the SATA drive with ext2 partition. 2. Configure U-Boot environment variable: setenv File_uImage setenv File_dtp setenv File_ramdisk saveenv 3.
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Boot System 6.3.4 Booting from an SD Card 1. Make sure that the kernel, dtb, and ramdisk are saved in the SD card with FAT partition. 2. Configure the U-Boot environment variable: setenv File_uImage setenv File_dtp setenv File_ramdisk saveenv 3. Initialize SD card: mmcinfo 4.
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Boot System 3. TFTP the files from the server to local memory, then boot: run vxboot 6.4 Using the Persistent Memory Feature Persistent memory means that the RAM's memory is not deleted during a reset. Power cycling, or by temporarily removing the power and then powering up the blade again, will delete the memory content. Persistent memory feature is enabled by default.
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Boot System 6.5 MVME2502 Specific U-Boot Commands Table 6-1 MVME2502 Specific U-Boot Commands 124 Command Description base Print or set address offset bdinfo Print board info structure boot Boot default, i.e., run 'bootcmd' bootd Boot default, i.e.
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Boot System Table 6-1 MVME2502 Specific U-Boot Commands (continued) Command Description help Print online help i2c I2C sub-system iminfo Print header information for application image imxtract Extract a part of a multi-image interrupts Enable or disable interrupts itest Return true/false on integer compare loadb Load binary file over serial line (kermit mode) loads Load S-Record file over serial line loady Load binary file over serial line (ymodem mode) loop Infinite loop on address ra
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Boot System Table 6-1 MVME2502 Specific U-Boot Commands (continued) 6.
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Boot System 3. Select SPI flash # 0: sf probe 0 4. Erase 0x90000 bytes starting at SPI address 0: sf erase 0 0x90000 5.
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Boot System 128 MVME2502 Installation and Use (6806800R96B)
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Chapter 7 Programming Model 7.1 Overview This chapter includes additional programming information for the MVME2502. 7.2 Reset Configuration The MVME2502 supports the power-on reset (POR) pin sampling method for processor reset configuration. Each option and the corresponding default setting are described in the following table.
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 6 Boot Sequence LGPL3/LFWP, LGPL5 11 CFG_BOOT_SEQ[1:0] = BOOT SEQUENCE DISABLED 7 Memory Debug Config DMA2_DACK0 1 Debug information from the DDR SDRAM controller is driven on the MSPCID and MDVAL signs (default) 8 DDR Debug Config DMA2_DDONE0 1 Debug information is not driven on ECC pins. ECC function in their normal mode (default).
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 18 ETSEC2 SGMII Mode LGPL1 1 eTSEC2 Ethernet interface operates in standard parallel interface mode and uses the TSEC_2’pins (default). 19 ETSEC3 SGMMI Mode TSEC_1588_ALARM _OUT2 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC_3’pins (default).
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 24 BOOT ROM Location TSEC1_TXD[6:4], TSEC1_TX_ER 011X On-chip boot ROM-SPI configuration (x=0), SDHC (x=1) 25 Host/Agent Config LWE1/LBS1, LA[18:19] 111 The processor acts as the host/root complex for all PCI-E/Serial Rapid IO interfaces (default). 26 I/O Port Select TSEC1_TXD[3:1], TSEC2_TX_ER 0010 PCI-E 1 (x1) (2.5 Gbps) SerDes lane 0 REMARKS PCI-E 2 (x1) (2.
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Programming Model 7.3 Interrupt Controller The MVME2502 uses the MPC8548E integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.
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Programming Model 7.4 I2C Bus Device Addressing The following table contains the I2C devices used for the MVME2502 and its assigned device address. Table 7-3 I2C Bus Device Addressing I2C Bus Address Device Function Size Notes 0x50 SPD 256 x 8 0x4C ADT 7461 Temperature Sensor N/A 0x68 DS 1375 real-time clock N/A 0x54 VPD 8192 x 8 1 0x52 User configuration 65536 x 8 1 0x53 User configuration 65536 x 8 1 0x55 RTM EEPROM 8192 X 8 1, 2 0x56 XMC EEPROM N/A 3 1.
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Programming Model Table 7-4 PHY Types and MII Management Bus Address 7.6 Ethernet Port Function / Location PHY Types PHY MIIM Address TSEC2 Gigabit Ethernet port routed to front or back panel, set by GBE_MUX_SEL in S2 BCM54616 7 TSEC3 Gigabit Ethernet port routed to back panel BCM54616 3 Other Software Considerations The following sections provide programming information in relation to various board components: 7.6.
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Programming Model 7.6.4 LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus.
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Programming Model SETA External address termination 0 - Access is terminated internally by the memory controller unless the external device asserts LGTA earlier to terminate the access. TRLX Timing Relaxed 0 - Normal timing is generated by the GPCM. EHTR Extended hold time on read accesses. 0 - The memory controller generates normal timing. No additional cycles are inserted EAD External address latch delay 0 - No additional bus clock cycles (LALE asserted for one bus clock cycle only) 7.
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Programming Model Table 7-6 Clock Distribution (continued) Device Clock Signal Frequency Clock Tree Source VIO BCM54616S SW_25MHZ_CLK 25Mhz ICS83905AGILF +3.3V XMC CLK_XMC1 100MHz ICS9FG108 DIFF QorIQ P2020 SD_REF_CLK 100MHz ICS9FG109 DIFF TSI384 CLK_PCIEC1 100MHz ICS9FG110 DIFF TSI384 CLK_PCIEC3 100MHz ICS9FG111 DIFF 88SE9125 CLK_88SE9125_PCIE_100MH Z 100MHz ICS9FG112 DIFF CPLD CLK_CPLD 1.8432MHz Oscillator +3.3V USB CLK_USB_1_24MHZ 24MHz Oscillator +3.
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Programming Model 7.7.2 Real Time Clock Input The RTC clock input is driven by a 1 MHz clock generated by the CPLD. This provides a fixed clock reference for the QorIQ P2020 PIC timers which the software can use as a known time reference. 7.7.3 Local Bus Controller Clock Divisor The local bus controller (LBC) clock output is connected to the CPLD for LBC bus transaction. It is also the source of 1 MHz (CPU_RTC) and CPLD tick timers.
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Programming Model 140 MVME2502 Installation and Use (6806800R96B)
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Appendix A A Replacing the Battery A.1 Replacing the Battery The figure below shows the location of the board battery.
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Replacing the Battery Figure A-2 142 Battery Location ENP2 Variant MVME2502 Installation and Use (6806800R96B)
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Replacing the Battery The battery provides seven years of data retention, summing up all periods of actual data use. Artesyn Embedded Technologies therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling. Board/System Damage  Incorrect replacement of lithium batteries can result in a hazardous explosion.
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Replacing the Battery Replacement Procedure To replace the battery, proceed as follows: 1. Remove the old battery. 2. Install the new battery with the plus sign (+) facing up. 3. Dispose of the old battery according to your country’s legislation and in an environmentally safe way.
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Appendix B B Related Documentation B.1 Artesyn Embedded Technologies - Embedded Computing Documentation The publications listed below are referenced in this manual. You can obtain electronic copies of Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation. 1. Go to www.artesyn.com/computing. 2. Under SUPPORT, click TECHNICAL DOCUMENTATION. 3.
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Related Documentation B.2 Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user manuals. As an additional help, a source for the listed document is provided. Please note that while these sources have been verified, the information is subject to change without notice. Table B-2 Manufacturers’ Publications B.3 Company Document Freescale Freescale Semiconductor, QorIQ™ P2020 Integrated Processor Reference Manual, Rev.
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Related Documentation Table B-3 Related Specifications Organization Document IEEE IEEE 802.3 LAN/MAN CSMA/CD Access Method IEEE 802.3-2005 IEEE Standard for a Common Mezzanine Card (CMC) Family IEEE Std 1386-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC) IEEE Std 1386.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-2001 Low Pin Count Interface Specification (LPC) Revision 1.
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Related Documentation 148 MVME2502 Installation and Use (6806800R96B)
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Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
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Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. Changes or modifications not expressly approved by Artesyn Embedded Technologies Embedded Technologies could void the user's authority to operate the equipment. Board products are tested in a representative system to show compliance with the above mentioned requirements.
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Safety Notes Make sure all software is completely shut down before removing power from the board or removing the board from the chassis. Product Damage Only use injector handles for board insertion to avoid damage to the front panel and/or PCB. Deformation of the front panel can cause an electrical short or other board malfunction. Product Damage Inserting or removing modules with power applied may result in damage to module components.
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Safety Notes Battery Board/System Damage Incorrect exchange of lithium batteries can result in a hazardous explosion. When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models. If the respective battery model is not available, contact your local Artesyn sales representative for the availability of alternative, officially approved battery models. Data Loss Exchanging the battery can result in loss of time settings.
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Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
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Sicherheitshinweise EMV Das Produkt wurde in einem Artesyn Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse B. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie Industriegebieten gewährleisten. Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung.
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Sicherheitshinweise Beschädigung von Schaltkreisen Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau des Produktes kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen. Bevor Sie das Produkt oder elektronische Komponenten berühren, vergewissern Sie sich, daß Sie in einem ESD-geschützten Bereich arbeiten. Fehlfunktion des Produktes Schalter, die mit 'Reserved' gekennzeichnet sind, können mit produktionsrelevanten Funktionen belegt sein.
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Sicherheitshinweise Kabel und Stecker Beschädigung des Produktes Bei den RJ-45-Steckern, die sich an dem Produkt befinden, handelt es sich entweder um Twisted-Pair-Ethernet (TPE) oder um E1/T1/J1-Stecker. Beachten Sie, dass ein versehentliches Anschließen einer E1/T1/J1-Leitung an einen TPE-Stecker das Produkt zerstören kann.  Kennzeichnen Sie deshalb TPE-Anschlüsse in der Nähe Ihres Arbeitsplatzes deutlich als Netzwerkanschlüsse.
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Sicherheitshinweise Datenverlust Wenn die Batterie wenig oder unzureichend mit Spannung versorgt wird, wird der RTC initialisiert. Tauschen Sie die Batterie aus, bevor sieben Jahre tatsächlicher Nutzung vergangen sind. Schäden an der Platine oder dem Batteriehalter Wenn Sie die Batterie mit einem Schraubendreher entfernen, können die Platine oder der Batteriehalter beschädigt werden. Um Schäden zu vermeiden, sollten Sie keinen Schraubendreher zum Ausbau der Batterie verwenden.
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Sicherheitshinweise 158 MVME2502 Installation and Use (6806800R96B)
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