Operating instructions

5.3.5 Output Stage
PB-16KOA (PB9A577)
Three FETs select the signal source to the output amplifier: the repro head
(Q120), sync repro (Q122), or the input to the record electronics (Q118).
The logic-selected signal is fed to the first stage of a dual Op Amp
(Operational Amplifier) (IC103A) and then to a bias trap, the second half of
the Op Amp (IC102B) and another bias trap. The output of the second bias
trap is fed to an Op Amp (IC104). Here the signal is divided into two, the one
being sent to IC104A and the other to IC105B, i.e., ACTIVE BALANCE
OUTPUT circuit. SW101 is a switch selecting between BAL and UNBAL.
Output to the VU meter is fed to the VU meter assembly through Q124
behind the second bias trap.
5.3.6 Input Circuitry
PB-16KOA (PB9A577)
A test signal input is provided on the Bias Control board. When a 1/4" (6.3
mm) phone plug is inserted in this jack, the signal is bussed to the TEST SIG.
input of every channel, and a DC voltage is applied to the TEST/LINE input.
FED Q202 then passes the test signal; FET Q201 is simultaneously turned
OFF, blocking the normal input signal. When a test signal is not plugged into
the Bias Control board, the normal signal path is as follows.
The channel input circuit adopts an ACTIVE BALANCE INPUT circuit in which
a transformer is not used. The signal applied to each channel passed. Past
through a fully balanced, dual amplifier input stage IC201A&B. The
unbalanced conversion takes place at IC202B then is carried out by FET
Q201. One of the outputs goes through RV202 (the Monitor Level
Calibration) to a Line Output Amp, while the other proceeds through RV201
to the output stage of the recording amplifier. IC204A and IC205A form the
High speed EQ recording amplifier, where as IC204B and IC205B form the
Low speed EQ recording amplifier. Adjustment of each EQ is provided at
VR203 and VR205. IC206A and IC206B form the PHASE COMP. circuit at
their own respective speeds.
15 ips NAB/IEC switching in the record circuitry is accomplished by FED
(Q203) being switched and letting IC203B perform the selected EQ curve.
This switching is a logic line derived from the bias control PCB at SW3.
NOTE: EQ circuit constant for the recording system is switchable.
Conversion of the constant for the change from NAB to IEC specification or
vice versa is accomplished by switching a miniature switch mounted on the
Bias Control PCB card. The signal supplied from EQ stage is fed to the last
stage of recording through Q205 or Q204 (Speed Select Gate). IC302 is the
MIX circuit for the mixed bias and audio signal. The bias current is supplied
to this MIX circuit after receiving adjustment of its ramping waveshape at
IC301.
15 ips high frequency pre-emphasis record phase compensation is provided
by IC206B, and adjusted by a 10-turn 10 kΩ potentiometer VR206. A 30 ips
high frequency pre-emphasis is provided by IC206A, and adjusted by 1 10-
turn, 10 kΩ potentiometer VR204. 15 ips EQ is selected when the logic turns
ON FET Q205, and 30 ips is selected when the logic turns off Q205 and turns
ON Q204.
The pre-emphasized audio from Q204 or Q205 feeds the active audio/bias
mixing circuitry.
Section 5 Maintenance
5 - 10
October 1990
MTR-90III Operation and Maintenance Manual