ARM Developer Suite ® Version 1.2 Assembler Guide Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Developer Suite Assembler Guide Copyright © 2000, 2001 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Change November 2000 A Release 1.1 November 2001 B Release 1.2 Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.
Contents ARM Developer Suite Assembler Guide Preface About this book .............................................................................................. vi Feedback ....................................................................................................... ix Chapter 1 Introduction 1.1 Chapter 2 Writing ARM and Thumb Assembly Language 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Chapter 3 Introduction ............................................................................
Contents 3.2 3.3 3.4 3.5 3.6 Chapter 4 ARM Instruction Reference 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Chapter 5 Thumb Thumb Thumb Thumb Thumb Thumb memory access instructions ........................................................... 5-4 arithmetic instructions ................................................................... 5-15 general data processing instructions ............................................ 5-22 branch instructions ................................................................
Preface This preface introduces the documentation for the ARM Developer Suite (ADS) assemblers and assembly language. It contains the following sections: • About this book on page vi • Feedback on page ix. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Preface About this book This book provides tutorial and reference information for the ADS assemblers (armasm, the free-standing assembler, and inline assemblers in the C and C++ compilers). It describes the command-line options to the assembler, the pseudo-instructions and directives available to assembly language programmers, and the ARM, Thumb®, and Vector Floating-point (VFP) instruction sets. Intended audience This book is written for all developers who are producing applications using ADS.
Preface Typographical conventions The following typographical conventions are used in this book: monospace Denotes text that can be entered at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. The underlined text can be entered instead of the full command or option name. monospace italic Denotes arguments to commands and functions where the argument is to be replaced by a specific value.
Preface • ADS Linker and Utilities Guide (ARM DUI 0151) • CodeWarrior IDE Guide (ARM DUI 0065) • AXD and armsd Debuggers Guide (ARM DUI 0066) • ADS Debug Target Guide (ARM DUI 0058) • ADS Developer Guide (ARM DUI 0056) • ARM Applications Library Programmer’s Guide (ARM DUI 0081). The following additional documentation is provided with the ARM Developer Suite: • ARM Architecture Reference Manual (ARM DDI 0100).
Preface Feedback ARM Limited welcomes feedback on both ADS and the documentation. Feedback on the ARM Developer Suite If you have any problems with ADS, please contact your supplier.
Preface x Copyright © 2000, 2001 ARM Limited. All rights reserved.
Chapter 1 Introduction This chapter introduces the assemblers provided with ARM Developer Suite (ADS) version 1.2. It contains the following sections: • About the ARM Developer Suite assemblers on page 1-2. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Introduction 1.1 About the ARM Developer Suite assemblers ARM Developer Suite (ADS) has: • a freestanding assembler, armasm • an optimizing inline assembler built into the C and C++ compilers. The language that these assemblers take as input is basically the same. However, there are limitations on what features of the language you can use in the inline assemblers. Refer to the Mixing C, C++, and Assembly Language chapter in ADS Developer Guide for further information on the inline assemblers.
Chapter 2 Writing ARM and Thumb Assembly Language This chapter provides an introduction to the general principles of writing ARM and Thumb assembly language.
Writing ARM and Thumb Assembly Language 2.1 Introduction This chapter gives a basic, practical understanding of how to write ARM and Thumb assembly language modules. It also gives information on the facilities provided by the ARM assembler (armasm). This chapter does not provide a detailed description of the ARM, Thumb, or VFP instruction sets. This information can be found in Chapter 4 ARM Instruction Reference, Chapter 5 Thumb Instruction Reference, and Chapter 6 Vector Floating-point Programming.
Writing ARM and Thumb Assembly Language 2.2 Overview of the ARM architecture This section gives a brief overview of the ARM architecture. ARM processors are typical of RISC processors in that they implement a load/store architecture. Only load and store instructions can access memory. Data processing instructions operate on register contents only. 2.2.1 Architecture versions The information and examples in this book assume that you are using a processor that implements ARM architecture v3 or above.
Writing ARM and Thumb Assembly Language 2.2.3 Processor mode ARM processors support up to seven processor modes, depending on the architecture version. These are: • User • FIQ - Fast Interrupt Request • IRQ - Interrupt Request • Supervisor • Abort • Undefined • System (ARM architecture v4 and above). All modes except User mode are referred to as privileged modes. Applications that require task protection usually execute in User mode.
Writing ARM and Thumb Assembly Language In User mode, r14 is used as a link register (lr) to store the return address when a subroutine call is made. It can also be used as a general-purpose register if the return address is stored on the stack. In the exception handling modes, r14 holds the return address for the exception, or a subroutine return address if subroutine calls are executed within an exception. r14 can be used as a general-purpose register if the return address is stored on the stack.
Writing ARM and Thumb Assembly Language 2.2.5 ARM instruction set overview All ARM instructions are 32 bits long. Instructions are stored word-aligned, so the least significant two bits of instruction addresses are always zero in ARM state. Some instructions use the least significant bit to determine whether the code being branched to is Thumb code or ARM code. See Chapter 4 ARM Instruction Reference for detailed information on the syntax of the ARM instruction set.
Writing ARM and Thumb Assembly Language Single register load and store instructions These instructions load or store the value of a single register from or to memory. They can load or store a 32-bit word or an 8-bit unsigned byte. In ARM architecture v4 and above they can also load or store a 16-bit unsigned halfword, or load and sign extend a 16-bit halfword or an 8-bit byte.
Writing ARM and Thumb Assembly Language 2.2.6 ARM instruction capabilities The following general points apply to ARM instructions: • Conditional execution • Register access • Access to the inline barrel shifter. Conditional execution Almost all ARM instructions can be executed conditionally on the value of the ALU status flags in the CPSR. You do not need to use branches to skip conditional instructions, although it can be better to do so when a series of instructions depend on the same condition.
Writing ARM and Thumb Assembly Language 2.2.7 Thumb instruction set overview The functionality of the Thumb instruction set is almost exactly a subset of the functionality of the ARM instruction set. The instruction set is optimized for production by a C or C++ compiler. All Thumb instructions are 16 bits long and are stored halfword-aligned in memory. Because of this, the least significant bit of the address of an instruction is always zero in Thumb state.
Writing ARM and Thumb Assembly Language Refer to Chapter 5 Thumb Instruction Reference for a complete list of the Thumb data processing instructions that can access the high registers. Access to the barrel shifter In Thumb state you can use the barrel shifter only in a separate operation, using an LSL, LSR, ASR, or ROR instruction. 2.2.
Writing ARM and Thumb Assembly Language Single register load and store instructions These instructions load or store the value of a single low register from or to memory. In Thumb state they can only access registers r0 to r7. Multiple register load and store instructions LDM and STM load from memory and store to memory any subset of the registers in the range r0 to r7. PUSH and POP instructions implement a full descending stack using the stack pointer (r13) as the base.
Writing ARM and Thumb Assembly Language 2.3 Structure of assembly language modules Assembly language is the language that the ARM assembler (armasm) parses and assembles to produce object code. This can be: • ARM assembly language • Thumb assembly language • a mixture of both. 2.3.
Writing ARM and Thumb Assembly Language Labels Labels are symbols that represent addresses. The address given by a label is calculated during assembly. The assembler calculates the address of a label relative to the origin of the section where the label is defined. A reference to a label within the same section can use the program counter plus or minus an offset. This is called program-relative addressing. Labels can be defined in a map.
Writing ARM and Thumb Assembly Language Constants Constants can be numeric, boolean, character or string: Numbers Numeric constants are accepted in three forms: • Decimal, for example, 123 • Hexadecimal, for example, 0x7B • n_xxx where: n is a base between 2 and 9 xxx is a number in that base. Boolean The Boolean constants TRUE and FALSE must be written as {TRUE} and {FALSE}.
Writing ARM and Thumb Assembly Language 2.3.2 An example ARM assembly language module Example 2-1 illustrates some of the core constituents of an assembly language module. The example is written in ARM assembly language. It is supplied as armex.s in the examples\asm subdirectory of ADS. Refer to Code examples on page 2-2 for instructions on how to assemble, link, and execute the example. The constituent parts of this example are described in more detail in the following sections.
Writing ARM and Thumb Assembly Language In an ARM assembly language source file, the start of a section is marked by the AREA directive. This directive names the section and sets its attributes. The attributes are placed after the name, separated by commas. Refer to AREA on page 7-52 for a detailed description of the syntax of the AREA directive. You can choose any name for your sections.
Writing ARM and Thumb Assembly Language 2.3.3 Calling subroutines To call subroutines, use a branch and link instruction. The syntax is: BL destination where destination is usually the label on the first instruction of the subroutine. destination can also be a program-relative or register-relative expression. Refer to B and BL on page 4-58 for further information. The BL instruction: • places the return address in the link register (lr) • sets pc to the address of the subroutine.
Writing ARM and Thumb Assembly Language 2.3.4 An example Thumb assembly language module Example 2-3 illustrates some of the core constituents of a Thumb assembly language module. It is based on subrout.s. It is supplied as thumbsub.s in the examples\asm subdirectory of the ADS. Refer to Code examples on page 2-2 for instructions on how to assemble, link, and execute the example.
Writing ARM and Thumb Assembly Language 2.4 Using the C preprocessor You can include the C preprocessor command #include in your assembly language source file. If you do this, you must preprocess the file using the C preprocessor, before using armasm to assemble it. See ADS Compilers and Libraries Guide. armasm correctly interprets #line commands in the resulting file. It can generate error messages and debug_line tables using the information in the #line commands.
Writing ARM and Thumb Assembly Language 2.5 Conditional execution In ARM state, each data processing instruction has an option to update ALU status flags in the Current Program Status Register (CPSR) according to the result of the operation. Add an S suffix to an ARM data processing instruction to make it update the ALU status flags in the CPSR. Do not use the S suffix with CMP, CMN, TST, or TEQ. These comparison instructions always update the flags. This is their only effect.
Writing ARM and Thumb Assembly Language 2.5.2 Execution conditions The relation of condition code suffixes to the N, Z, C and V flags is shown in Table 2-1.
Writing ARM and Thumb Assembly Language 2.5.3 Using conditional execution in ARM state You can use conditional execution of ARM instructions to reduce the number of branch instructions in your code. This improves code density. Branch instructions are also expensive in processor cycles. On ARM processors without branch prediction hardware, it typically takes three processor cycles to refill the processor pipeline each time a branch is taken.
Writing ARM and Thumb Assembly Language Because of the number of branches, the code is seven instructions long. Every time a branch is taken, the processor must refill the pipeline and continue from the new location. The other instructions and non-executed branches use a single cycle each.
Writing ARM and Thumb Assembly Language Table 2-3 All instructions conditional r0: a r1: b Instruction Cycles (ARM7) 1 2 CMP r0, r1 1 1 2 SUBGT r0,r0,r1 1 (not executed) 1 1 SUBLT r1,r1,r0 1 1 1 BNE gcd 3 1 1 CMP r0,r1 1 1 1 SUBGT r0,r0,r1 1 (not executed) 1 1 SUBLT r1,r1,r0 1 (not executed) 1 1 BNE gcd 1 (not executed) Total = 10 Converting to Thumb Because B is the only Thumb instruction that can be executed conditionally, the gcd algorithm must be written with conditi
Writing ARM and Thumb Assembly Language 2.6 Loading constants into registers You cannot load an arbitrary 32-bit immediate constant into a register in a single instruction without performing a data load from memory. This is because ARM instructions are only 32 bits long. Thumb instructions have a similar limitation. You can load any 32-bit value into a register with a data load, but there are more direct and efficient ways to load many commonly-used constants.
Writing ARM and Thumb Assembly Language 2.6.1 Direct loading with MOV and MVN In ARM state, you can use the MOV and MVN instructions to load a range of 8-bit constant values directly into a register: • MOV can load any 8-bit constant value, giving a range of 0x0 to 0xFF (0-255). It can also rotate these values by any even number. Table 2-4 shows the range of values that this provides. • MVN can load the bitwise complement of these values.
Writing ARM and Thumb Assembly Language Direct loading with MOV in Thumb state In Thumb state you can use the MOV instruction to load constants in the range 0-255. You cannot generate constants outside this range because: • The Thumb MOV instruction does not provide inline access to the barrel shifter. Constants cannot be right-rotated as they can in ARM state. • The Thumb MVN instruction can act only on registers and not on constant values.
Writing ARM and Thumb Assembly Language Placing literal pools The assembler places a literal pool at the end of each section. These are defined by the AREA directive at the start of the following section, or by the END directive at the end of the assembly. The END directive at the end of an included file does not signal the end of a section. In large sections the default literal pool can be out of range of one or more LDR instructions.
Writing ARM and Thumb Assembly Language LDR MOV LTORG r2, =0xFFFFFFFF pc, lr LDR r3, =0x55555555 ; => MVN R2, #0 ; Literal Pool 1 contains ; literal Ox55555555 func2 ; LDR r4, =0x66666666 MOV LargeTable SPACE => LDR R3, [PC, #offset to Literal Pool 1] If this is uncommented it fails, because Literal Pool 2 is out of reach ; ; ; ; Starting at the current location, clears a 4200 byte area of memory to zero Literal Pool 2 is empty pc, lr 4200 END 2.6.
Writing ARM and Thumb Assembly Language 2.7 Loading addresses into registers It is often necessary to load an address into a register. You might need to load the address of a variable, a string constant, or the start location of a jump table. Addresses are normally expressed as offsets from the current pc or other register. This section describes two methods for loading an address into a register: • load the register directly, see Direct loading with ADR and ADRL.
Writing ARM and Thumb Assembly Language Note The label used with ADR or ADRL must be within the same code section. The assembler faults references to labels that are out of range in the same section. The linker faults references to labels that are out of range in other code sections. In Thumb state, ADR can generate word-aligned addresses only. ADRL is not available in Thumb code. Use it only in ARM code.
Writing ARM and Thumb Assembly Language Implementing a jump table with ADR Example 2-7 on page 2-33 shows ARM code that implements a jump table. It is supplied as jump.s in the examples\asm subdirectory of ADS. Refer to Code examples on page 2-2 for instructions on how to assemble, link, and execute the example. The ADR pseudo-instruction loads the address of the jump table. In the example, the function arithfunc takes three arguments and returns a result in r0.
Writing ARM and Thumb Assembly Language Example 2-7 ARM code jump table num AREA CODE32 EQU ENTRY Jump, CODE, READONLY 2 start MOV MOV MOV BL stop MOV LDR SWI arithfunc CMP MOVHS ADR LDR JumpTable DCD DCD r0, #0 r1, #3 r2, #2 arithfunc r0, #0x18 r1, =0x20026 0x123456 DoAdd r0, pc, r0, pc, DoSub ADD MOV SUB MOV END ARM DUI 0068B r0, pc, r3, pc, #num lr JumpTable [r3,r0,LSL#2] ; ; ; ; ; ; Name this block of code Following code is ARM code Number of entries in jump table Mark first instruction t
Writing ARM and Thumb Assembly Language Converting to Thumb Example 2-8 shows the implementation of the jump table converted to Thumb code. Most of the Thumb version is the same as the ARM code. The differences are commented in the Thumb version. In Thumb state, you cannot: • increment the base register of LDR and STR instructions • load a value into the pc using an LDR instruction • do an inline shift of a value held in a register.
Writing ARM and Thumb Assembly Language 2.7.2 Loading addresses with LDR Rd, = label The LDR Rd,= pseudo-instruction can load any 32-bit constant into a register. See Loading with LDR Rd, =const on page 2-27. It also accepts program-relative expressions such as labels, and labels with offsets. The assembler converts an LDR r0,=label pseudo-instruction by: • Placing the address of label in a literal pool (a portion of memory embedded in the code to hold constant values).
Writing ARM and Thumb Assembly Language LDR r1, =Darea + 12 LDR r2, =Darea + 6000 MOV LTORG pc,lr LDR r3, =Darea + 6000 ; LDR r4, =Darea + 6004 MOV SPACE pc, lr 8000 ; ; ; ; ; ; ; Literal Pool 1] => LDR R1,[PC, #offset into Literal Pool 1] => LDR R2, [PC, #offset into Literal Pool 1] Return Literal Pool 1 ; ; ; ; ; ; ; ; ; ; ; => LDR r3, [PC, #offset into Literal Pool 1] (sharing with previous literal) If uncommented produces an error as Literal Pool 2 is out of range Return Starting at the
Writing ARM and Thumb Assembly Language An LDR Rd, =label example: string copying Example 2-10 shows an ARM code routine that overwrites one string with another string. It uses the LDR pseudo-instruction to load the addresses of the two strings from a data section. The following are particularly significant: DCB The DCB directive defines one or more bytes of store. In addition to integer values, DCB accepts quoted strings. Each character of the string is placed in a consecutive byte.
Writing ARM and Thumb Assembly Language Converting to Thumb There is no post-indexed addressing mode for Thumb LDR and STR instructions. Because of this, you must use an ADD instruction to increment the address register after the LDR and STR instructions. For example: LDRB ADD 2-38 r2, [r1] r1, #1 ; load register 2 ; increment the address in ; register 1. Copyright © 2000, 2001 ARM Limited. All rights reserved.
Writing ARM and Thumb Assembly Language 2.8 Load and store multiple register instructions The ARM and Thumb instruction sets include instructions that load and store multiple registers to and from memory. Multiple register transfer instructions provide an efficient way of moving the contents of several registers to and from memory. They are most often used for block copy and for stack operations at subroutine entry and exit.
Writing ARM and Thumb Assembly Language 2.8.1 ARM LDM and STM instructions The load (or store) multiple instruction loads (stores) any subset of the 16 general-purpose registers from (to) memory, using a single instruction. Syntax The syntax of the LDM instructions is: LDM{cond}address-mode Rn{!},reg-list{^} where: is an optional condition code. Refer to Conditional execution on page 2-20 for more information. cond address-mode specifies the addressing mode of the instruction.
Writing ARM and Thumb Assembly Language Usage See Implementing stacks with LDM and STM on page 2-42 and Block copy with LDM and STM on page 2-44. 2.8.2 LDM and STM addressing modes There are four different addressing modes. The base register can be incremented or decremented by one word for each register in the operation, and the increment or decrement can occur before or after the operation. The suffixes for these options are: IA Increment after. IB Increment before. DA Decrement after.
Writing ARM and Thumb Assembly Language 2.8.3 Implementing stacks with LDM and STM The load and store multiple instructions can update the base register. For stack operations, the base register is usually the stack pointer, r13. This means that you can use load and store multiple instructions to implement push and pop operations for any number of registers in a single instruction.
Writing ARM and Thumb Assembly Language Stacking registers for nested subroutines Stack operations are very useful at subroutine entry and exit. At the start of a subroutine, any working registers required can be stored on the stack, and at exit they can be popped off again. In addition, if the link register is pushed onto the stack at entry, additional subroutine calls can safely be made without causing the return address to be lost.
Writing ARM and Thumb Assembly Language 2.8.4 Block copy with LDM and STM Example 2-11 is an ARM code routine that copies a set of words from a source location to a destination by copying a single word at a time. It is supplied as word.s in the examples\asm subdirectory of the ADS. Refer to Code examples on page 2-2 for instructions on how to assemble, link, and execute the example.
Writing ARM and Thumb Assembly Language Example 2-12 num AREA EQU ENTRY Block, CODE, READONLY 20 ; name this block of code ; set number of words to be copied ; mark the first instruction to call LDR LDR MOV MOV MOVS BEQ STMFD LDMIA STMIA SUBS BNE LDMFD r0, =src r1, =dst r2, #num sp, #0x400 r3,r2, LSR #3 copywords sp!, {r4-r11} r0!, {r4-r11} r1!, {r4-r11} r3, r3, #1 octcopy sp!, {r4-r11} ANDS BEQ LDR STR SUBS BNE MOV LDR SWI r2, r2, #7 stop r3, [r0], #4 r3, [r1], #4 r2, r2, #1 wordcopy r0, #0x18 r1,
Writing ARM and Thumb Assembly Language 2.8.5 Thumb LDM and STM instructions The Thumb instruction set contains two pairs of multiple-register transfer instructions: • LDM and STM for block memory transfers • PUSH and POP for stack operations. LDM and STM These instructions can be used to load or store any subset of the low registers from or to memory. The base register is always updated at the end of the multiple register transfer instruction. You must specify the ! character.
Writing ARM and Thumb Assembly Language Example 2-13 num AREA EQU ENTRY Tblock, CODE, READONLY 20 MOV ADR BX sp, #0x400 r0, start + 1 r0 header CODE16 ; ; ; ; ; ; ; ; ; Name this block of code Set number of words to be copied Mark first instruction to execute The first instruction to call Set up stack pointer (r13) Processor starts in ARM state, so small ARM code header used to call Thumb main program Subsequent instructions are Thumb start LDR LDR MOV blockcopy LSR BEQ PUSH quadcopy LDMIA STMIA
Writing ARM and Thumb Assembly Language 2.9 Using macros A macro definition is a block of code enclosed between MACRO and MEND directives. It defines a name that can be used instead of repeating the whole block of code. This has two main uses: • to make it easier to follow the logic of the source code, by replacing a block of code with a single, meaningful name • to avoid repeating a block of code several times. Refer to MACRO and MEND on page 7-27 for more details. 2.9.
Writing ARM and Thumb Assembly Language 2.9.2 Unsigned integer division macro example Example 2-14 shows a macro that performs an unsigned integer division. It takes four parameters: $Bot The register that holds the divisor. $Top The register that holds the dividend before the instructions are executed. After the instructions are executed, it holds the remainder. $Div The register where the quotient of the division is placed. It can be NULL ("") if only the remainder is required.
Writing ARM and Thumb Assembly Language The macro checks that no two parameters use the same register. It also optimizes the code produced if only the remainder is required. To avoid multiple definitions of labels if DivMod is used more than once in the assembler source, the macro uses local labels (90, 91). Refer to Local labels on page 2-13 for more information.
Writing ARM and Thumb Assembly Language 2.10 Describing data structures with MAP and FIELD directives You can use the MAP and FIELD directives to describe data structures. These directives are always used together. Data structures defined using MAP and FIELD: • are easily maintainable • can be used to describe multiple instances of the same structure • make it easy to access data efficiently. The MAP directive specifies the base address of the data structure.
Writing ARM and Thumb Assembly Language 2.10.1 Relative maps To access data more than 4KB away from the current instruction, you can use a register-relative instruction, such as: LDR r4,[r9,#offset] offset is limited to 4096, so r9 must already contain a value within 4KB of the address of the data.
Writing ARM and Thumb Assembly Language 2.10.2 Register-based maps In many cases, you can use the same register as the base register every time you access a data structure. You can include the name of the register in the base address of the map. Example 2-17 shows such a register-based map. The labels defined in the map include the register.
Writing ARM and Thumb Assembly Language 2.10.3 Program-relative maps You can use the program counter (r15) as the base register for a map. In this case, each STM or LDM instruction must be within 4KB of the data item it addresses, because the offset is limited to 4KB. The data structure must be in the same section as the instructions, because otherwise there is no guarantee that the data items will be within range after linking. Example 2-18 shows a program fragment with such a map.
Writing ARM and Thumb Assembly Language 2.10.4 Finding the end of the allocated data You can use the FIELD directive with an operand of 0 to label a location within a structure. The location is labeled, but the location counter is not incremented. The size of the data structure defined in Example 2-19 depends on the values of MaxStrLen and ArrayLen. If these values are too large, the structure overruns the end of available memory.
Writing ARM and Thumb Assembly Language 2.10.5 Forcing correct alignment You are likely to have problems if you include some character variables in the data structure, as in Example 2-20. This is because a lot of words are misaligned.
Writing ARM and Thumb Assembly Language Example 2-21 StartOfData EndOfData Char Char2 Char3 EndOfChars Padding Integer Integer2 String Array BitMask EndOfUsedData ARM DUI 0068B EQU EQU MAP FIELD FIELD FIELD FIELD FIELD FIELD FIELD FIELD FIELD FIELD FIELD ASSERT 0x1000 0x2000 StartOfData 1 1 1 0 (-EndOfChars):AND:3 4 4 MaxStrLen ArrayLen*8 4 0 EndOfUsedData <= EndOfData Copyright © 2000, 2001 ARM Limited. All rights reserved.
Writing ARM and Thumb Assembly Language 2.10.6 Using register-based MAP and FIELD directives Register-based MAP and FIELD directives define register-based symbols. There are two main uses for register-based symbols: • defining structures similar to C structures • gaining faster access to memory sections described by non register-based MAP and FIELD directives. Defining register-based symbols Register-based symbols can be very useful, but you must be careful when using them.
Writing ARM and Thumb Assembly Language Setting up a C-type structure There are two stages to using structures in C: 1. Declaring the fields that the structure contains. 2. Generating the structure in memory and using it. For example, the following typedef statement defines a point structure that contains three float fields named x, y and z, but it does not allocate any memory.
Writing ARM and Thumb Assembly Language Making faster access possible To gain faster access to a section of memory: 1. Describe the memory section as a structure. 2. Use a register to address the structure. For example, consider the definitions in Example 2-22.
Writing ARM and Thumb Assembly Language Example 2-23 on page 2-60 contains separate LDR pseudo-instructions to load the address of each of the data items. Each LDR pseudo-instruction is converted to a separate instruction by the assembler. However, it is possible to access the entire data section with a single LDR pseudo-instruction. Example 2-24 shows how to do this. Both speed and code size are improved.
Writing ARM and Thumb Assembly Language If you use the same technique for a section of memory containing memory-mapped I/O (or whose absolute addresses must not change for other reasons), you must take care to keep the code maintainable. One method is to add comments to the code warning maintainers to take care when modifying the definitions. A better method is to use definitions of the absolute addresses to control the register-based definitions.
Writing ARM and Thumb Assembly Language 2.10.7 Using two register-based structures Sometimes you need to operate on two structures of the same type at the same time. For example, if you want the equivalent of the pseudo-code: newloc.x = oldloc.x + (value in r0); newloc.y = oldloc.y + (value in r1); newloc.z = oldloc.z + (value in r2); The base register needs to point alternately to the oldloc structure and to the newloc one. Repeatedly changing the base register would be inefficient.
Writing ARM and Thumb Assembly Language 2.10.8 Avoiding problems with MAP and FIELD directives Using MAP and FIELD directives can help you to produce maintainable data structures. However, this is only true if the order the elements are placed in memory is not important to either the programmer or the program. You can have problems if you load or store multiple elements of a structure in a single instruction.
Writing ARM and Thumb Assembly Language Example 2-27 on page 2-64 loads the first six items in the array Misc_data. The array is a single element and therefore covers contiguous memory locations. No one is likely to want to split it into separate arrays in the future.
Writing ARM and Thumb Assembly Language 2.11 Using frame directives You must use frame directives to describe the way that your code uses the stack if you want to be able to do either of the following: • debug your application using stack unwinding • use either flat or call-graph profiling. Refer to Frame description directives on page 7-33 for details of these directives. The assembler uses these directives to insert DWARF2 debug frame information into the object file in ELF format that it produces.
Chapter 3 Assembler Reference This chapter provides general reference material on the ARM assemblers. It contains the following sections: • Command syntax on page 3-2 • Format of source lines on page 3-8 • Predefined register and coprocessor names on page 3-9 • Built-in variables on page 3-10 • Symbols on page 3-12 • Expressions, literals, and operators on page 3-18. This chapter does not explain how to write ARM assembly language.
Assembler Reference 3.1 Command syntax This section relates only to armasm. The inline assemblers are part of the C and C++ compilers, and have no command syntax of their own. The armasm command line is case-insensitive, except in filenames, and where specified. Invoke the ARM assembler using this command: armasm [-16|-32] [-apcs [none|[/qualifier[/qualifier[...
Assembler Reference /ropi specifies that the content of inputfile is read-only position-independent. The default is /noropi. /pic is a synonym for /ropi. /nopic is a synonym for /noropi. /rwpi specifies that the content of inputfile is read-write position-independent. The default is /norwpi. /pid is a synonym for /rwpi. /nopid is a synonym for /norwpi. /swstackcheck specifies that the code in inputfile carries out software stack-limit checking.
Assembler Reference instructs the assembler to write source file dependency lists to inputfile.d. -md -errors errorfile instructs the assembler to output error messages to errorfile. -fpu name this option selects the target floating-point unit (FPU) architecture. If you specify this option it overrides any implicit FPU set by the -cpu option. Floating-point instructions produce either errors or warnings if assembled for the wrong target FPU.
Assembler Reference instructs the assembler to display a summary of the assembler command-line options. -help -i dir [,dir]… adds directories to the source file search path so that arguments to GET, INCLUDE, or INCBIN directives do not need to be fully qualified (see GET or INCLUDE on page 7-61). instructs the assembler to keep local labels in the symbol table of the object file, for use by the debugger (see KEEP on page 7-64).
Assembler Reference -nocache turns off source caching. By default the assembler caches source files on the first pass and reads them from memory on the second pass. -noesc instructs the assembler to ignore C-style escaped special characters, such as \n and \t. -noregs instructs the assembler not to predefine register names. See Predefined register and coprocessor names on page 3-9 for a list of predefined register names. -nowarn turns off warning messages. -o filename names the output object file.
Assembler Reference Note Avoiding large multiple register transfers increases code size and decreases performance slightly. Avoiding large multiple register transfers has no significant benefit for cached systems or processors with a write buffer. Avoiding large multiple register transfers also has no benefit for systems without zero wait-state memory, or for systems with slow peripheral devices.
Assembler Reference 3.2 Format of source lines The general form of source lines in an ARM assembly language module is: {symbol} {instruction|directive|pseudo-instruction} {;comment} All three sections of the source line are optional. Instructions cannot start in the first column. They must be preceded by white space even if there is no preceding symbol. You can write directives in all upper case, as in this manual. Alternatively, you can write directives in all lower case.
Assembler Reference 3.3 Predefined register and coprocessor names All register and coprocessor names are case-sensitive. 3.3.
Assembler Reference 3.4 Built-in variables Table 3-1 lists the built-in variables defined by the ARM assembler. Table 3-1 Built-in variables {PC} or . Address of current instruction. {VAR} or @ Current value of the storage area location counter. {TRUE} Logical constant true. {FALSE} Logical constant false. {OPT} Value of the currently-set listing option. The OPT directive can be used to save the current listing option, force a change in it, or restore its original value.
Assembler Reference |ads$version| must be all lower case. The other built-in variables can be upper-case, lower-case, or mixed. 3.4.1 Determining the armasm version at assembly time The built-in variable {ARMASM$VERSION} can be used to distinguish between versions of armasm from ADS1.0 onwards. However, previous versions of armasm did not have this built-in variable. If you need to build both ADS and SDT versions of your code, you can test for the built-in variable |ads$version|.
Assembler Reference 3.5 Symbols You can use symbols to represent variables, addresses, and numeric constants. Symbols representing addresses are also called labels. See: • Variables on page 3-13 • Numeric constants on page 3-13 • Labels on page 3-15 • Local labels on page 3-16. 3.5.1 Symbol naming rules The following general rules apply to symbol names: • You can use uppercase letters, lowercase letters, numeric characters, or the underscore character in symbol names.
Assembler Reference 3.5.2 Variables The value of a variable can be changed as assembly proceeds. Variables are of three types: • numeric • logical • string. The type of a variable cannot be changed. The range of possible values of a numeric variable is the same as the range of possible values of a numeric constant or numeric expression (see Numeric constants and Numeric expressions on page 3-20). The possible values of a logical variable are {TRUE} or {FALSE} (see Logical expressions on page 3-23).
Assembler Reference 3.5.4 Assembly time substitution of variables You can use a string variable for a whole line of assembly language, or any part of a line. Use the variable with a $ prefix in the places where the value is to be substituted for the variable. The dollar character instructs the assembler to substitute the string into the source code line before checking the syntax of the line. Numeric and logical variables can also be substituted.
Assembler Reference 3.5.5 Labels Labels are symbols representing the addresses in memory of instructions or data. They can be program-relative, register-relative, or absolute. Program-relative labels These represent the program counter, plus or minus a numeric constant. Use them as targets for branch instructions, or to access small items of data embedded in code sections. You can define program-relative labels using a label on an instruction or on one of the data definition directives.
Assembler Reference 3.5.6 Local labels A local label is a number in the range 0-99, optionally followed by a name. The same number can be used for more than one local label in an ELF section. Local labels are typically used for loops and conditional code within a routine, or for small subroutines that are only used locally. They are particularly useful in macros (see MACRO and MEND on page 7-27). Use the ROUT directive to limit the scope of local labels (see ROUT on page 7-68).
Assembler Reference If routname is specified in either a label or a reference to a label, the assembler checks it against the name of the nearest preceding ROUT directive. If it does not match, the assembler generates an error message and the assembly fails. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Assembler Reference 3.
Assembler Reference 3.6.1 String expressions String expressions consist of combinations of string literals, string variables, string manipulation operators, and parentheses. See: • String literals • Variables on page 3-13 • Unary operators on page 3-26 • String manipulation operators on page 3-28 • SETA, SETL, and SETS on page 7-7. Characters that cannot be placed in string literals can be placed in string expressions using the :CHR: unary operator. Any ASCII character from 0 to 255 is allowed.
Assembler Reference 3.6.3 Numeric expressions Numeric expressions consist of combinations of numeric constants, numeric variables, ordinary numeric literals, binary operators, and parentheses. See: • Numeric constants on page 3-13 • Variables on page 3-13 • Numeric literals on page 3-21 • Binary operators on page 3-28 • SETA, SETL, and SETS on page 7-7.
Assembler Reference 3.6.4 Numeric literals Numeric literals can take any of the following forms: • decimal-digits 0xhexadecimal-digits &hexadecimal-digits • n_base-n-digits 'character' where decimal-digits is a sequence of characters using only the digits 0 to 9. hexadecimal-digits is a sequence of characters using only the digits 0 to 9 and the letters A to F or a to f. n_ is a single digit between 2 and 9 inclusive, followed by an underscore character.
Assembler Reference 3.6.5 Floating-point literals Floating-point literals can take any of the following forms: {-}digits E{-}digits {-}{digits}.digits{E{-}digits} 0xhexdigits &hexdigits digits are sequences of characters using only the digits 0 to 9. You can write E in uppercase or lowercase. These forms correspond to normal floating-point notation. hexdigits are sequences of characters using only the digits 0 to 9 and the letters A to F or a to f.
Assembler Reference 3.6.6 Register-relative and program-relative expressions A register-relative expression evaluates to a named register plus or minus a numeric constant (see MAP on page 7-15). A program-relative expression evaluates to the program counter (pc), plus or minus a numeric constant. It is normally a label combined with a numeric expression. Example data 3.6.
Assembler Reference 3.6.9 Operator precedence The assembler includes an extensive set of operators for use in expressions. Many of the operators resemble their counterparts in high-level languages such as C (see Unary operators on page 3-26 and Binary operators on page 3-28). There is a strict order of precedence in their evaluation: 1. Expressions in parentheses are evaluated first. 2. Operators are applied in precedence order. 3. Adjacent unary operators are evaluated from right to left. 4.
Assembler Reference Table 3-2 Operator precedence in armasm armasm precedence equivalent C operators + - :AND: :OR: :EOR: + - & | = > >= < <= /= <> == > >= < <= != :LAND: :LOR: :LEOR: && || Table 3-3 Operator precedence in C C precedence unary operators * / % + - (as binary operators) << >> < <= > >= == != & ^ | && || The highest precedence operators are at the top of the list. The highest precedence operators are evaluated first. Operators of equal precedence are evaluated from left to right.
Assembler Reference 3.6.10 Unary operators Unary operators have the highest precedence and are evaluated first. A unary operator precedes its operand. Adjacent operators are evaluated from right to left. Table 3-4 lists the unary operators. Table 3-4 Unary operators Operator Usage Description ? ?A Number of bytes of executable code generated by line defining symbol A.
Assembler Reference Example of use of :SB_OFFSET_19_12: and :SB_OFFSET_11_ 0 MyIndex EQU 0 AREA area1, CODE LDR IP, [SB, #0] LDR IP, [IP, #MyIndex] ADD IP, IP, # :SB_OFFSET_19_12: label LDR PC, [IP, # :SB_OFFSET_11_0: label] AREA area2, DATA label IMPORT FunctionAddress DCD FunctionAddress END These operators can only be used in ADD and LDR instructions. They can only be used in the way shown. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Assembler Reference 3.6.11 Binary operators Binary operators are written between the pair of subexpressions they operate on. Binary operators have lower precedence than unary operators. Binary operators appear in this section in order of precedence. Note The order of precedence is not the same as in C, see Operator precedence on page 3-24. Multiplicative operators Multiplicative operators have the highest precedence of all binary operators. They act only on numeric expressions.
Assembler Reference Shift operators Shift operators act on numeric expressions, shifting or rotating the first operand by the amount specified by the second. Table 3-7 shows the shift operators. Table 3-7 Shift operators Operator Usage Explanation ROL A:ROL:B Rotate A left by B bits ROR A:ROR:B Rotate A right by B bits SHL A:SHL:B Shift A left by B bits SHR A:SHR:B Shift A right by B bits Note SHR is a logical shift and does not propagate the sign bit.
Assembler Reference Relational operators Table 3-9 shows the relational operators. These act on two operands of the same type to produce a logical value. The operands can be one of: • numeric • program-relative • register-relative • strings. Strings are sorted using ASCII ordering. String A is less than string B if it is a leading substring of string B, or if the left-most character in which the two strings differ is less in string A than in string B.
Assembler Reference Boolean operators These are the operators with the lowest precedence. They perform the standard logical operations on their operands. In all three cases both A and B must be expressions that evaluate to either {TRUE} or {FALSE}. Table 3-10 shows the Boolean operators.
Assembler Reference 3-32 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Chapter 4 ARM Instruction Reference This chapter describes the ARM instructions that are supported by the ARM assembler.
ARM Instruction Reference Table 4-1 Location of ARM instructions Mnemonic Brief description Page Architecturea ADC, ADD Add with carry, Add page 4-27 All AND Logical AND page 4-30 All B Branch page 4-58 All BIC Bit clear page 4-30 All BKPT Breakpoint page 4-76 5 BL Branch with link page 4-58 All BLX Branch, link and exchange page 4-60 5Tb BX Branch and exchange page 4-59 4Tb CDP, CDP2 Coprocessor data operation page 4-63 2, 5 CLZ Count leading zeroes page 4-38 5
ARM Instruction Reference Table 4-1 Location of ARM instructions (continued) Mnemonic Brief description Page Architecturea MUL Multiply page 4-40 2 MVN Move not page 4-32 All ORR Logical OR page 4-30 All PLD Cache preload page 4-20 5Ed QADD, QDADD, QDSUB, QSUB Saturating arithmetic page 4-55 5ExPe RSB, RSC, SBC Reverse sub, Reverse sub with carry, Sub with carry page 4-27 All SMLAL Signed multiply-accumulate (64 <= 32 x 32 + 64) page 4-42 Mf SMLALxy Signed multiply-accumula
ARM Instruction Reference 4.1 Conditional execution Almost all ARM instructions can include an optional condition code. This is shown in syntax descriptions as {cond}. An instruction with a condition code is only executed if the condition code flags in the CPSR meet the specified condition. The condition codes that you can use are shown in Table 4-2.
ARM Instruction Reference Some instructions update a subset of the flags. The other flags are unchanged by these instructions. Details are specified in the descriptions of the instructions. You can execute an instruction conditionally, based upon the flags set in another instruction, either: • immediately after the instruction which updated the flags • after any number of intervening instructions that have not updated the flags. For further information, see Conditional execution on page 2-20. 4.1.
ARM Instruction Reference 4.2 ARM memory access instructions This section contains the following subsections: • LDR and STR, words and unsigned bytes on page 4-7 Load register and store register, 32-bit word or 8-bit unsigned byte. • LDR and STR, halfwords and signed bytes on page 4-12 Load register, signed 8-bit bytes and signed and unsigned 16-bit halfwords. Store register, 16-bit halfwords. • LDR and STR, doublewords on page 4-15 Load two consecutive registers and store two consecutive registers.
ARM Instruction Reference 4.2.1 LDR and STR, words and unsigned bytes Load register and store register, 32-bit word or 8-bit unsigned byte. Byte loads are zero-extended to 32 bits. Syntax Both LDR and STR have four possible forms: • zero offset • pre-indexed offset • program-relative • post-indexed offset.
ARM Instruction Reference FlexOffset is a flexible offset applied to the value in Rn (see Flexible offset syntax on page 4-9). label is a program-relative expression. See Register-relative and program-relative expressions on page 3-23 for more information. label must be within ±4KB of the current instruction. is an optional suffix. If ! is present, the address including the offset is written back into Rn. You cannot use the ! suffix if Rn is r15.
ARM Instruction Reference Flexible offset syntax Both pre-indexed and post-indexed offsets can be either of the following: #expr {-}Rm{, shift} where: - is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn. expr is an expression evaluating to an integer in the range –4095 to +4095. This is often a numeric constant (see examples below). Rm is a register containing a value to be used as the offset. Rm must not be r15.
ARM Instruction Reference Address alignment for word transfers In most circumstances, you must ensure that addresses for 32-bit transfers are 32-bit word-aligned. If your system has a system coprocessor (cp15), you can enable alignment checking. Non word-aligned 32-bit transfers cause an alignment exception if alignment checking is enabled. If your system does not have a system coprocessor (cp15), or alignment checking is disabled: • For STR, the specified address is rounded down to a multiple of four.
ARM Instruction Reference Saving from r15 In general, avoid saving from r15 if possible. If you do save from r15, the value saved is the address of the current instruction, plus an implementation-defined constant. The constant is always the same for a particular processor.
ARM Instruction Reference 4.2.2 LDR and STR, halfwords and signed bytes Load register, signed 8-bit bytes and signed and unsigned 16-bit halfwords. Store register, 16-bit halfwords. Signed loads are sign-extended to 32 bits. Unsigned halfword loads are zero-extended to 32 bits. Syntax These instructions have four possible forms: • zero offset • pre-indexed offset • program-relative • post-indexed offset.
ARM Instruction Reference label is a program-relative expression. See Register-relative and program-relative expressions on page 3-23 for more information. label must be within ±255 bytes of the current instruction. Offset is an offset applied to the value in Rn (see Offset syntax). ! is an optional suffix. If ! is present, the address including the offset is written back into Rn. You cannot use the ! suffix if Rn is r15. Zero offset The value in Rn is used as the address for the transfer.
ARM Instruction Reference is a register containing a value to be used as the offset. Rm The offset syntax is the same for LDR and STR, doublewords on page 4-15. Address alignment for halfword transfers The address must be even for halfword transfers. If your system has a system coprocessor (cp15), you can enable alignment checking. Non halfword-aligned 16-bit transfers cause an alignment exception if alignment checking is enabled.
ARM Instruction Reference 4.2.3 LDR and STR, doublewords Load two consecutive registers and store two consecutive registers, 64-bit doubleword. Syntax These instructions have four possible forms: • zero offset • pre-indexed offset • program-relative • post-indexed offset. The syntax of the four forms are, in the same order: op{cond}D Rd, [Rn] op{cond}D Rd, [Rn, Offset]{!} op{cond}D Rd, label op{cond}D Rd, [Rn], Offset where: op is either LDR or STR.
ARM Instruction Reference Zero offset The value in Rn is used as the address for the transfer. Pre-indexed offset The offset is applied to the value in Rn before the transfers take place. The result is used as the memory address for the transfers. If the ! suffix is used, the address is written back into Rn. Program-relative This is an alternative version of the pre-indexed form. The assembler calculates the offset from the PC for you, and generates a pre-indexed instruction with the PC as Rn.
ARM Instruction Reference If your system has a system coprocessor, you can enable alignment checking. Non doubleword-aligned 64-bit transfers cause an alignment exception if alignment checking is enabled. Architectures These instructions are available in E variants of ARM architecture v5 and above. Examples LDRD LDRMID STRD STRD LDREQD r6,[r11] r4,[r7],r2 r4,[r9,#24] r0,[r9,-r2]! r8,abc4 Incorrect examples LDRD STRD STRD ARM DUI 0068B r1,[r6] r14,[r9,#36] r2,[r3],r6 ; Rd must be even.
ARM Instruction Reference 4.2.4 LDM and STM Load and store multiple registers. Any combination of registers r0 to r15 can be transferred. Syntax op{cond}mode Rn{!}, reglist{^} where: 4-18 op is either LDM or STM. cond is an optional condition code (see Conditional execution on page 4-4).
ARM Instruction Reference Non word-aligned addresses These instructions ignore bits [1:0] of the address. (On a system with a system coprocessor, if alignment checking is enabled, nonzero values in these bits cause an alignment exception.) Loading to r15 A load to r15 (the program counter) causes a branch to the instruction at the address loaded. In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set.
ARM Instruction Reference 4.2.5 PLD Cache preload. Syntax PLD [Rn{, FlexOffset}] where: Rn is the register on which the memory address is based. FlexOffset is an optional flexible offset applied to the value in Rn. FlexOffset can be either of the following: #expr {-}Rm{, shift} where: - is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn. expr is an expression evaluating to an integer in the range –4095 to +4095.
ARM Instruction Reference Usage Use PLD to hint to the memory system that there is likely to be a load from the specified address within the next few instructions. The memory system can use this to speed up later memory accesses. Alignment There are no alignment restrictions on the address. If a system control coprocessor (cp15) is present then it will not generate an alignment exception for any PLD instruction. Architectures This instruction is available in E variants of ARM architecture v5 and above.
ARM Instruction Reference 4.2.6 SWP Swap data between registers and memory. Use SWP to implement semaphores. Syntax SWP{cond}{B} Rd, Rm, [Rn] where: cond is an optional condition code (see Conditional execution on page 4-4). B is an optional suffix. If B is present, a byte is swapped. Otherwise, a 32-bit word is swapped. Rd is an ARM register. Data from memory is loaded into Rd. Rm is an ARM register. The contents of Rm is saved to memory. Rm can be the same register as Rd.
ARM Instruction Reference 4.
ARM Instruction Reference 4.3.1 Flexible second operand Most ARM general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Syntax Operand2 has two possible forms: #immed_8r Rm{, shift} where: immed_8r is an expression evaluating to a numeric constant. The constant must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word (but see Instruction substitution on page 4-26).
ARM Instruction Reference ASR Arithmetic shift right by n bits divides the value contained in Rm by 2n, if the contents are regarded as a two’s complement signed integer. The original bit[31] is copied into the left-hand n bits of the register. LSR and LSL Logical shift right by n bits divides the value contained in Rm by 2n, if the contents are regarded as an unsigned integer. The left-hand n bits of the register are set to 0.
ARM Instruction Reference 31 30 1 0 ... Carry Flag ... Figure 4-2 RRX The carry flag The carry flag is updated to the last bit shifted out of Rm, if the instruction is any one of the following: • MOV, MVN, AND, ORR, EOR or BIC, if you use the S suffix • TEQ or TST, for which no S suffix is required. Instruction substitution Certain pairs of instructions (ADD and SUB, ADC and SBC, AND and BIC, MOV and MVN, CMP and CMN) are equivalent except for the negation or logical inversion of immed_8r.
ARM Instruction Reference 4.3.2 ADD, SUB, RSB, ADC, SBC, and RSC Add, subtract, and reverse subtract, each with or without carry. Syntax op{cond}{S} Rd, Rn, Operand2 where: op is one of ADD, SUB, RSB, ADC, SBC, or RSC. cond is an optional condition code (see Conditional execution on page 4-4). S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 4-4). Rd is the ARM register for the result.
ARM Instruction Reference Condition flags If S is specified, these instructions update the N, Z, C and V flags according to the result. Use of r15 If you use r15 as Rn, the value used is the address of the instruction plus 8. If you use r15 as Rd: • Execution branches to the address corresponding to the result. • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer Guide).
ARM Instruction Reference ADDS ADC r4,r0,r2 r5,r1,r3 ; adding the least significant words ; adding the most significant words These instructions subtract one 96-bit integer from another: SUBS SBCS SBC r3,r6,r9 r4,r7,r10 r5,r8,r11 For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid: SUBS SBCS SBC ARM DUI 0068B r6,r6,r9 r9,r2,r1 r2,r8,r11 Copyright © 2000, 2001 ARM Limited.
ARM Instruction Reference 4.3.3 AND, ORR, EOR, and BIC Logical AND, OR, Exclusive OR and Bit Clear. Syntax op{cond}{S} Rd, Rn, Operand2 where: op is one of AND, ORR, EOR, or BIC. cond is an optional condition code (see Conditional execution on page 4-4). S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 4-4). Rd is the ARM register for the result. Rn is the ARM register holding the first operand.
ARM Instruction Reference Use of r15 If you use r15 as Rn, the value used is the address of the instruction plus 8. If you use r15 as Rd: • Execution branches to the address corresponding to the result. • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer Guide). Caution Do not use the S suffix when using r15 as Rd in User mode or System mode.
ARM Instruction Reference 4.3.4 MOV and MVN Move and Move Not. Syntax MOV{cond}{S} Rd, Operand2 MVN{cond}{S} Rd, Operand2 where: cond is an optional condition code (see Conditional execution on page 4-4). S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 4-4). Rd is the ARM register for the result. Operand2 is a flexible second operand.
ARM Instruction Reference Use of r15 If you use r15 as Rn, the value used is the address of the instruction plus 8. If you use r15 as Rd: • Execution branches to the address corresponding to the result. • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer Guide). Caution Do not use the S suffix when using r15 as Rd in User mode or System mode.
ARM Instruction Reference 4.3.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code (see Conditional execution on page 4-4). Rn is the ARM register holding the first operand. Operand2 is a flexible second operand. See Flexible second operand on page 4-24 for details of the options. Usage These instructions compare the value in a register with Operand2.
ARM Instruction Reference Architectures These instructions are available in all versions of the ARM architecture. Examples CMP CMN CMPGT r2,r9 r0,#6400 r13,r7,LSL #2 Incorrect example CMP ARM DUI 0068B r2,r15,ASR r0 ; r15 not allowed with register ; controlled shift Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.3.6 TST and TEQ Test and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code (see Conditional execution on page 4-4). Rn is the ARM register holding the first operand. Operand2 is a flexible second operand. See Flexible second operand on page 4-24 for details of the options. Usage These instructions test the value in a register against Operand2.
ARM Instruction Reference Architectures These instructions are available in all versions of the ARM architecture. Examples TST TEQEQ TSTNE r0,#0x3F8 r10,r9 r1,r5,ASR r1 Incorrect example TEQ ARM DUI 0068B r15,r1,ROR r0 ; r15 not allowed with register ; controlled shift Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.3.7 CLZ Count Leading Zeroes. Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code (see Conditional execution on page 4-4). Rd is the ARM register for the result. Rd must not be r15. Rm is the operand register. Usage The CLZ instruction counts the number of leading zeroes in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit 31 is set.
ARM Instruction Reference 4.4 ARM multiply instructions This section contains the following subsections: • MUL and MLA on page 4-40 Multiply and multiply-accumulate (32-bit by 32-bit, bottom 32-bit result). • UMULL, UMLAL, SMULL and SMLAL on page 4-42 Unsigned and signed long multiply and multiply accumulate (32-bit by 32-bit, 64-bit accumulate or result). • SMULxy on page 4-44 Signed multiply (16-bit by 16-bit, 32-bit result).
ARM Instruction Reference 4.4.1 MUL and MLA Multiply and multiply-accumulate (32-bit by 32-bit, bottom 32-bit result). Syntax MUL{cond}{S} Rd, Rm, Rs MLA{cond}{S} Rd, Rm, Rs, Rn where: cond is an optional condition code (see Conditional execution on page 4-4). S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 4-4). Rd is the ARM register for the result.
ARM Instruction Reference Examples MUL MLA MULS MULLT MLAVCS r10,r2,r5 r10,r2,r1,r5 r0,r2,r2 r2,r3,r2 r8,r6,r3,r8 Incorrect examples MUL MLA ARM DUI 0068B r15,r0,r3 r1,r1,r6 ; use of r15 not allowed ; Rd cannot be the same as Rm Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.4.2 UMULL, UMLAL, SMULL and SMLAL Unsigned and signed long multiply and multiply accumulate (32-bit by 32-bit, 64-bit accumulate or result). Syntax Op{cond}{S} RdLo, RdHi, Rm, Rs where: Op is one of UMULL, UMLAL, SMULL, or SMLAL. cond is an optional condition code (see Conditional execution on page 4-4). S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 4-4).
ARM Instruction Reference Condition flags If S is specified, these instructions: • update the N and Z flags according to the result • corrupt the C and V flags in ARM architecture v4 and earlier • do not affect the C or V flags in ARM architecture v5 and later. Architectures These instructions are available in ARM architecture v3M, and ARM architecture v4 and above except xM variants.
ARM Instruction Reference 4.4.3 SMULxy Signed multiply (16-bit by 16-bit, 32-bit result). Syntax SMUL{cond} Rd, Rm, Rs where: is either B or T. B means use the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm. is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs. cond is an optional condition code (see Conditional execution on page 4-4). Rd is the ARM register for the result.
ARM Instruction Reference Incorrect examples SMULBT SMULTTS ARM DUI 0068B r15,r2,r0 r0,r6,r2 ; use of r15 not allowed ; use of S suffix not allowed Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.4.4 SMLAxy Signed multiply-accumulate (16-bit by 16-bit, 32-bit accumulate). Syntax SMLA{cond} Rd, Rm, Rs, Rn where: is either B or T. B means use the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm. is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs. cond is an optional condition code (see Conditional execution on page 4-4). Rd is the ARM register for the result.
ARM Instruction Reference Architectures This instruction is available in all E variants of ARM architecture v5 and above. Examples SMLATT SMLABBNE SMLABT r8,r1,r0,r8 r0,r2,r1,r10 r0,r0,r3,r5 Incorrect examples SMLATB SMLATTS ARM DUI 0068B r0,r7,r8,r15 r0,r6,r2 ; use of r15 not allowed ; use of S suffix not allowed Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.4.5 SMULWy Signed multiply (32-bit by 16-bit, top 32-bit result). Syntax SMULW{cond} Rd, Rm, Rs where: is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs. cond is an optional condition code (see Conditional execution on page 4-4). Rd is the ARM register for the result. Rm, Rs are the ARM registers holding the operands. r15 cannot be used for any of Rd, Rm, or Rs.
ARM Instruction Reference 4.4.6 SMLAWy Signed multiply-accumulate (32-bit by 16-bit, top 32-bit accumulate). Syntax SMLAW{cond} Rd, Rm, Rs, Rn where: is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs. cond is an optional condition code (see Conditional execution on page 4-4). Rd is the ARM register for the result. Rm, Rs are the ARM registers holding the values to be multiplied.
ARM Instruction Reference Architectures This instruction is available in all E variants of ARM architecture v5 and above. Examples SMLAWB SMLAWTVS r2,r4,r7,r1 r0,r0,r9,r2 Incorrect examples SMLAWT SMLAWBS 4-50 r15,r9,r3,r1 r0,r4,r5,r1 ; use of r15 not allowed ; use of S suffix not allowed Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.4.7 SMLALxy Signed multiply-accumulate (16-bit by 16-bit, 64-bit accumulate). Syntax SMLAL{cond} RdLo, RdHi, Rm, Rs where: is either B or T. B means use the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm. is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs. cond is an optional condition code (see Conditional execution on page 4-4).
ARM Instruction Reference Examples SMLALTB SMLALBTVS r2,r3,r7,r1 r0,r1,r9,r2 Incorrect examples SMLALTT SMLALBBS 4-52 r8,r9,r3,r15 r0,r1,r5,r2 ; use of r15 not allowed ; use of S suffix not allowed Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.4.8 MIA, MIAPH, and MIAxy XScale coprocessor 0 instructions. Multiply with internal accumulate (32-bit by 32-bit, 40-bit accumulate). Multiply with internal accumulate, packed halfwords (16-bit by 16-bit twice, 40-bit accumulate). Multiply with internal accumulate (16-bit by 16-bit, 40-bit accumulate). Syntax MIA{cond} Acc, Rm, Rs MIAPH{cond} Acc, Rm, Rs MIA{cond} Acc, Rm, Rs where: cond is an optional condition code (see Conditional execution on page 4-4).
ARM Instruction Reference The MIAxy instruction multiplies the signed integer from the selected half of Rs by the signed integer from the selected half of Rm, and adds the 32-bit result to the 40-bit value in Acc. Condition flags These instructions do not affect any flags. Note These instructions cannot raise an exception. If overflow occurs on these instructions, the result wraps round without any warning. Architectures These instructions are only available in XScale.
ARM Instruction Reference 4.5 ARM saturating arithmetic instructions These operations are saturating (SAT). This means that if overflow occurs: • the Q flag is set • if the full result would be less than –231, the result returned is –231 • if the full result would be greater than 231–1, the result returned is 231–1. The Q flag can also be set by two other instructions (see SMLAxy on page 4-46 and SMLAWy on page 4-49), but these instructions do not saturate. 4.5.
ARM Instruction Reference Note All values are treated as two’s complement signed integers by these instructions. Condition flags These instructions do not affect the N, Z, C, and V flags. If saturation occurs, they set the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS on page 4-73). Note These instructions never clear the Q flag, even if saturation does not occur. To clear the Q flag, use an MSR instruction (see MSR on page 4-74).
ARM Instruction Reference 4.6 ARM branch instructions This section contains the following subsections: • B and BL on page 4-58 Branch, and Branch with Link • BX on page 4-59 Branch and exchange instruction set. • BLX on page 4-60 Branch with Link and exchange instruction set. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.6.1 B and BL Branch, and Branch with Link. Syntax B{cond} label BL{cond} label where: cond is an optional condition code (see Conditional execution on page 4-4). label is a program-relative expression. See Register-relative and program-relative expressions on page 3-23 for more information. Usage The B instruction causes a branch to label. The BL instruction copies the address of the next instruction into r14 (lr, the link register), and causes a branch to label.
ARM Instruction Reference 4.6.2 BX Branch, and optionally exchange instruction set. Syntax BX{cond} Rm where: cond is an optional condition code (see Conditional execution on page 4-4). Rm is an ARM register containing the address to branch to. Bit 0 of Rm is not used as part of the address. If bit 0 of Rm is set, the instruction sets the T flag in the CPSR, and the code at the destination is interpreted as Thumb code. If bit 0 of Rm is clear, bit 1 must not be set.
ARM Instruction Reference 4.6.3 BLX Branch with Link, and optionally exchange instruction set. This instruction has two alternative forms: • an unconditional branch with link to a program-relative address • a conditional branch with link to an absolute address held in a register. Syntax BLX{cond} Rm BLX label where: cond is an optional condition code (see Conditional execution on page 4-4). Rm is an ARM register containing the address to branch to. Bit 0 of Rm is not used as part of the address.
ARM Instruction Reference Architectures This instruction is available in all T variants of ARM architecture v5 and above. Examples BLX BLXNE BLX r2 r0 thumbsub Incorrect example BLXMI ARM DUI 0068B thumbsub ; BLX label cannot be conditional Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.7 ARM coprocessor instructions This section does not describe Vector Floating-point instructions (see Chapter 6 Vector Floating-point Programming).
ARM Instruction Reference 4.7.1 CDP, CDP2 Coprocessor data operations. Syntax CDP{cond} coproc, opcode1, CRd, CRn, CRm{, opcode2} CDP2 coproc, opcode1, CRd, CRn, CRm{, opcode2} where: cond is an optional condition code (see Conditional execution on page 4-4). coproc is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0-15. opcode1 is a coprocessor-specific opcode. CRd, CRn, CRm are coprocessor registers.
ARM Instruction Reference 4.7.2 MCR, MCR2, MCRR Move to coprocessor from ARM registers. Depending on the coprocessor, you might be able to specify various operations in addition. Syntax MCR{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2} MCR2 coproc, opcode1, Rd, CRn, CRm{, opcode2} MCRR{cond} coproc, opcode1, Rd, Rn, CRm where: cond is an optional condition code (see Conditional execution on page 4-4). coproc is the name of the coprocessor the instruction is for.
ARM Instruction Reference 4.7.3 MRC, MRC2 Move to ARM register from coprocessor. Depending on the coprocessor, you might be able to specify various operations in addition. Syntax MRC{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2} MRC2 coproc, opcode1, Rd, CRn, CRm{, opcode2} where: cond is an optional condition code (see Conditional execution on page 4-4). coproc is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0-15.
ARM Instruction Reference 4.7.4 MRRC Move to two ARM registers from coprocessor. Depending on the coprocessor, you might be able to specify various operations in addition. Syntax MRRC{cond} coproc, opcode, Rd, Rn, CRm where: cond is an optional condition code (see Conditional execution on page 4-4). coproc is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0-15. opcode is a coprocessor-specific opcode.
ARM Instruction Reference 4.7.5 LDC, STC Transfer data between memory and coprocessor. Syntax These instructions have three possible forms: • zero offset • pre-indexed offset • post-indexed offset. The syntax of the three forms, in the same order, are: op{cond}{L} coproc, CRd, [Rn] op{cond}{L} coproc, CRd, [Rn, #{-}offset]{!} op{cond}{L} coproc, CRd, [Rn], #{-}offset where: op is either LDC or STC. cond is an optional condition code (see Conditional execution on page 4-4).
ARM Instruction Reference Architectures LDC and STC are available in ARM architecture versions 2 and above. 4-68 Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.7.6 LDC2, STC2 Transfer data between memory and coprocessor, alternative instructions. Syntax These instructions have three possible forms: • zero offset • pre-indexed offset • post-indexed offset. The syntax of the three forms, in the same order, are: op coproc, CRd, [Rn] op coproc, CRd, [Rn, #{-}offset]{!} op coproc, CRd, [Rn], #{-}offset where: op is either LDC2 or STC2. coproc is the name of the coprocessor the instruction is for.
ARM Instruction Reference Architectures LDC2 and STC2 are available in ARM architecture versions 5 and above. 4-70 Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.8 Miscellaneous ARM instructions This section contains the following subsections: • SWI on page 4-72 Software interrupt • MRS on page 4-73 Move the contents of the CPSR or SPSR to a general-purpose register • MSR on page 4-74 Load specified fields of the CPSR or SPSR with an immediate constant, or from the contents of a general-purpose register • BKPT on page 4-76 Breakpoint • MAR, MRA on page 4-77 XScale coprocessor 0 instructions.
ARM Instruction Reference 4.8.1 SWI Software interrupt. Syntax SWI{cond} immed_24 where: cond is an optional condition code (see Conditional execution on page 4-4). immed_24 is an expression evaluating to an integer in the range 0-224–1 (a 24-bit integer). Usage The SWI instruction causes a SWI exception.
ARM Instruction Reference 4.8.2 MRS Move the contents of the CPSR or SPSR to a general-purpose register. Syntax MRS{cond} Rd, psr where: is an optional condition code (see Conditional execution on page 4-4). is the destination register. Rd must not be r15. is either CPSR or SPSR. cond Rd psr Usage Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to change processor mode, or to clear the Q flag.
ARM Instruction Reference 4.8.3 MSR Load specified fields of the CPSR or SPSR with an immediate constant, or from the contents of a general-purpose register. Syntax MSR{cond} _, #immed_8r MSR{cond} _, Rm where: is an optional condition code (see Conditional execution on page 4-4). cond is either CPSR or SPSR. specifies the field or fields to be moved.
ARM Instruction Reference Example MSR CPSR_f, r5 ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.8.4 BKPT Breakpoint. Syntax BKPT immed_16 where: immed_16 is an expression evaluating to an integer in the range 0-65535 (a 16-bit integer). immed_16 is ignored by ARM hardware, but can be used by a debugger to store additional information about the breakpoint. Usage The BKPT instruction causes the processor to enter Debug mode. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
ARM Instruction Reference 4.8.5 MAR, MRA XScale coprocessor 0 instructions. Transfer between two general-purpose registers and a 40-bit internal accumulator. Syntax MAR{cond} Acc, RdLo, RdHi MRA{cond} RdLo, RdHi, Acc where: cond is an optional condition code (see Conditional execution on page 4-4). Acc is the internal accumulator. The standard name is accx, where x is an integer in the range 0-n. The value of n depends on the processor. It is 0 for current processors.
ARM Instruction Reference 4.9 ARM pseudo-instructions The ARM assembler supports a number of pseudo-instructions that are translated into the appropriate combination of ARM or Thumb instructions at assembly time.
ARM Instruction Reference 4.9.1 ADR ARM pseudo-instruction Load a program-relative or register-relative address into a register. Syntax ADR{cond} register,expr where: cond is an optional condition code. register is the register to load. expr is a program-relative or register-relative expression that evaluates to: • a non word-aligned address within ±255 bytes • a word-aligned address within ±1020 bytes. More distant addresses can be used if the alignment is 16 bytes or more.
ARM Instruction Reference 4.9.2 ADRL ARM pseudo-instruction Load a program-relative or register-relative address into a register. It is similar to the ADR pseudo-instruction. ADRL can load a wider range of addresses than ADR because it generates two data processing instructions. Note ADRL is not available when assembling Thumb instructions. Use it only in ARM code. Syntax ADR{cond}L register,expr where: cond is an optional condition code. register is the register to load.
ARM Instruction Reference If expr is program-relative, it must evaluate to an address in the same code section as the ADRL pseudo-instruction. Otherwise, it might be out of range after linking. Example start ARM DUI 0068B MOV ADRL r0,#10 r4,start + 60000 ; => ADD r4,pc,#0xe800 ; ADD r4,r4,#0x254 Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM Instruction Reference 4.9.3 LDR ARM pseudo-instruction Load a register with either: • a 32-bit constant value • an address. Note This section describes the LDR pseudo-instruction only. See ARM memory access instructions on page 4-6 for information on the LDR instruction. Syntax LDR{cond} register,=[expr | label-expr] where: cond is an optional condition code. register is the register to be loaded.
ARM Instruction Reference Usage The LDR pseudo-instruction is used for two main purposes: • To generate literal constants when an immediate value cannot be moved into a register because it is out of range of the MOV and MVN instructions • To load a program-relative or external address into a register. The address remains valid regardless of where the linker places the ELF section containing the LDR. Note An address loaded in this way is fixed at link time, so the code is not position-independent.
ARM Instruction Reference 4.9.4 NOP ARM pseudo-instruction NOP generates the preferred ARM no-operation code. The following instruction might be used, but this is not guaranteed: MOV r0, r0 Syntax NOP Usage NOP cannot be used conditionally. Not executing a no-operation is the same as executing it, so conditional execution is not required. ALU status flags are unaltered by NOP. 4-84 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Chapter 5 Thumb Instruction Reference This chapter describes the Thumb instructions that are provided by the ARM assembler and the inline assemblers in the ARM C and C++ compilers.
Thumb Instruction Reference Table 5-1 Location of Thumb instructions and pseudo-instructions Instruction mnemonic Brief description Page Architecturea ADC Add with carry page 5-21 4T ADD Add page 5-15 4T ADR Load address (pseudo-instruction) page 5-40 - AND Logical AND page 5-23 4T ASR Arithmetic shift right page 5-24 4T B Branch page 5-32 4T BIC Bit clear page 5-23 4T BKPT Breakpoint page 5-38 5T BL Branch with link page 5-34 4T BLX Branch with link and exchange in
Thumb Instruction Reference Table 5-1 Location of Thumb instructions and pseudo-instructions (continued) Instruction mnemonic Brief description Page Architecturea ROR Rotate right page 5-24 4T SBC Subtract with carry page 5-21 4T STMIA Store multiple registers, increment after page 5-13 4T STR Store register, immediate offset page 5-5 4T STR Store register, register offset page 5-7 4T STR Store register, pc or sp relative page 5-9 4T SUB Subtract page 5-15 4T SWI Software i
Thumb Instruction Reference 5.1 Thumb memory access instructions This section contains the following subsections: • LDR and STR, immediate offset on page 5-5 Load Register and Store Register. Address in memory specified as an immediate offset from a value in a register. • LDR and STR, register offset on page 5-7 Load Register and Store Register. Address in memory specified as a register-based offset from a value in a register.
Thumb Instruction Reference 5.1.1 LDR and STR, immediate offset Load Register and Store Register. Address in memory specified as an immediate offset from a value in a register. Syntax op Rd, [Rn, #immed_5x4] opH Rd, [Rn, #immed_5x2] opB Rd, [Rn, #immed_5x1] where: is either: op LDR STR Load register Store register. H is a parameter specifying an unsigned halfword transfer. B is a parameter specifying an unsigned byte transfer. Rd is the register to be loaded or stored.
Thumb Instruction Reference Address alignment for word and halfword transfers The address must be divisible by 4 for word transfers, and by 2 for halfword transfers. If your system has a system coprocessor (cp15), you can enable alignment checking. Non-aligned transfers cause an alignment exception if alignment checking is enabled. If your system does not have a system coprocessor (cp15), or alignment checking is disabled: • A non-aligned load corrupts Rd.
Thumb Instruction Reference 5.1.2 LDR and STR, register offset Load Register and Store Register. Address in memory specified as a register-based offset from a value in a register.
Thumb Instruction Reference Address alignment for word and halfword transfers The address must be divisible by 4 for word transfers, and by 2 for halfword transfers. If your system has a system coprocessor (cp15), you can enable alignment checking. Non-aligned transfers cause an alignment exception if alignment checking is enabled. If your system does not have a system coprocessor (cp15), or alignment checking is disabled: • A non-aligned load corrupts Rd. • A non-aligned save corrupts memory.
Thumb Instruction Reference 5.1.3 LDR and STR, pc or sp relative Load Register and Store Register. Address in memory specified as an immediate offset from a value in the pc or the sp. Note There is no pc-relative STR instruction. Syntax LDR Rd, [pc, #immed_8x4] LDR Rd, label LDR Rd, [sp, #immed_8x4] STR Rd, [sp, #immed_8x4] where: Rd is the register to be loaded or stored. Rd must be in the range r0 to r7. immed_8x4 is the offset.
Thumb Instruction Reference If your system does not have a system coprocessor (cp15), or alignment checking is disabled: • A non-aligned load corrupts Rd. • A non-aligned save corrupts four bytes in memory. The corrupted location in memory is [address AND NOT b11]. Architectures These instructions are available in all T variants of the ARM architecture.
Thumb Instruction Reference 5.1.4 PUSH and POP Push low registers, and optionally the lr, onto the stack. Pop low registers, and optionally the pc, off the stack. Syntax PUSH {reglist} POP {reglist} PUSH {reglist, lr} POP {reglist, pc} where: reglist is a comma-separated list of low registers or low-register ranges. Note The braces in the syntax description are part of the instruction format. They do not indicate that the register list is optional. There must be at least one register in the list.
Thumb Instruction Reference POP {reglist, pc} This instruction causes a branch to the address popped off the stack into the pc. This is usually a return from a subroutine, where the lr was pushed onto the stack at the start of the subroutine. In ARM architecture version 5T and above: • if bits[1:0] of the value loaded to the pc are b00, the processor changes to ARM state • bits[1:0] must not have the value b10.
Thumb Instruction Reference 5.1.5 LDMIA and STMIA Load and store multiple registers. Syntax op Rn!, {reglist} where: is either: op LDMIA STMIA Load multiple, increment after Store multiple, increment after. Rn is the register containing the base address. Rn must be in the range r0-r7. reglist is a comma-separated list of low registers or low-register ranges. Note The braces in the syntax description are part of the instruction format. They do not indicate that the register list is optional.
Thumb Instruction Reference Examples LDMIA LDMIA STMIA STMIA r3!, r5!, r0!, r3!, {r0,r4} {r0-r7} {r6,r7} {r3,r5,r7} Incorrect examples 5-14 LDMIA r3!,{r0,r9} ; high registers not allowed STMIA r5!, {} STMIA r5!,{r1-r6} ; value stored from r5 is unpredictable ; must be at least one register ; in list Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.2 Thumb arithmetic instructions This section contains the following subsections: • ADD and SUB, low registers on page 5-16 Add and subtract. • ADD, high or low registers on page 5-18 Add values in registers, one or both of them in the range r8 to r15. • ADD and SUB, sp on page 5-19 Increment or decrement sp by an immediate constant. • ADD, pc or sp relative on page 5-20 Add an immediate constant to the value from sp or pc, and place the result into a low register.
Thumb Instruction Reference 5.2.1 ADD and SUB, low registers Add and subtract. There are three forms of these instructions that operate on low registers. You can: • add or subtract the contents of two registers, and place the result in a third register • add a small integer to, or subtract it from, the value in a register, and place the result in a different register • add a larger integer to, or subtract it from, the value in a register, and return the result to the same register.
Thumb Instruction Reference Note An ADD instruction with a negative value for expr3 or expr8 assembles to the corresponding SUB instruction with a positive constant. A SUB instruction with a negative value for expr3 or expr8 assembles to the corresponding ADD instruction with a positive constant. Be aware of this when looking at disassembly listings. Restrictions Rd, Rn, and Rm must all be low registers (that is, in the range r0 to r7). Condition flags These instructions update the N, Z, C, and V flags.
Thumb Instruction Reference 5.2.2 ADD, high or low registers Add values in registers, returning the result to the first operand register. Syntax ADD Rd, Rm where: Rd is the destination register. It is also used for the first operand. Rm is a register containing the second operand. Usage This instruction adds the values in Rd and Rm, and places the result in Rd.
Thumb Instruction Reference 5.2.3 ADD and SUB, sp Increment or decrement sp by an immediate constant. Syntax ADD sp, #expr SUB sp, #expr where: is an expression that evaluates (at assembly time) to a multiple of 4 in the range –508 to +508. expr Usage This instruction adds the value of expr to the value from Rp, and places the result in Rd. Note An ADD instruction with a negative value for expr assembles to the corresponding SUB instruction with a positive constant.
Thumb Instruction Reference 5.2.4 ADD, pc or sp relative Add an immediate constant to the value from sp or pc, and place the result into a low register. Syntax ADD Rd, Rp, #expr where: Rd is the destination register. Rd must be in the range r0-r7. Rp is either sp or pc. expr is an expression that evaluates (at assembly time) to a multiple of 4 in the range 0-1020. Usage This instruction adds the value of expr to the value from Rp, and places the result in Rd.
Thumb Instruction Reference 5.2.5 ADC, SBC, and MUL Add with carry, Subtract with carry, and Multiply. Syntax op Rd, Rm where: op is one of ADC, SBC, or MUL. Rd is the destination register. It also contains the first operand. Rm is a register containing the second operand. Usage ADC adds the values in Rd and Rm, together with the carry flag, and places the result in Rd. Use this to synthesize multiword addition.
Thumb Instruction Reference 5.3 Thumb general data processing instructions This section contains the following subsections: • AND, ORR, EOR, and BIC on page 5-23 Bitwise logical operations. • ASR, LSL, LSR, and ROR on page 5-24 Shift and rotate operations. • CMP and CMN on page 5-26 Compare and Compare Negative. • MOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate. • TST on page 5-30 Test bits. 5-22 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.3.1 AND, ORR, EOR, and BIC Bitwise logical operations. Syntax op Rd, Rm where: op is one of AND, ORR, EOR, or BIC. Rd is the destination register. It also contains the first operand. Rd must be in the range r0-r7. Rm is the register containing the second operand. Rm must be in the range r0-r7. Usage These instructions perform a bitwise logical operation on the contents of Rd and Rm, and place the result in Rd.
Thumb Instruction Reference 5.3.2 ASR, LSL, LSR, and ROR Shift and rotate operations. These instructions can use a value contained in a register, or an immediate shift value. Syntax op Rd, Rs op Rd, Rm, #expr where: op is one of: ASR Arithmetic Shift Right. Register contents are treated as two’s complement signed integers. The sign bit is copied into vacated bits. LSL Logical Shift Left. Vacated bits are cleared. LSR Logical Shift Right. Vacated bits are cleared. ROR Rotate Right.
Thumb Instruction Reference Register-controlled shift These instructions take the value from Rd, apply the shift to it, and place the result back into Rd. Only the least significant byte of Rs is used for the shift value. For all these instructions except ROR: • if the shift is 32, Rd is cleared, and the last bit shifted out remains in the C flag • if the shift is greater than 32, Rd and the C flag are cleared.
Thumb Instruction Reference 5.3.3 CMP and CMN Compare and Compare Negative. Syntax CMP Rn, #expr CMP Rn, Rm CMN Rn, Rm where: Rn is the register containing the first operand. expr is an expression that evaluates (at assembly time) to an integer in the range 0-255. Rm is a register containing the second operand. Usage These instructions update the condition flags, but do not place a result in a register. The CMP instruction subtracts the value of expr, or the value in Rm, from the value in Rn.
Thumb Instruction Reference Examples CMP r2,#255 CMP r7,r12 CMN r1,r5 ; high register IS allowed with CMP Rn,Rm Incorrect examples CMP r2,#508 CMP r9,#24 CMN r0,r10 ARM DUI 0068B ; immediate value out of range ; high register not allowed with #expr ; high register not allowed with CMN Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.3.4 MOV, MVN, and NEG Move, Move NOT, and Negate. Syntax MOV Rd, #expr MOV Rd, Rm MVN Rd, Rm NEG Rd, Rm where: Rd is the destination register. expr is an expression that evaluates (at assembly time) to an integer in the range 0-255. Rm is the source register. Usage The MOV instruction places #expr, or the value from Rm, in Rd. The MVN instruction takes the value in Rm, performs a bitwise logical NOT operation on the value, and places the result in Rd.
Thumb Instruction Reference Condition flags MOV Rd,#expr and MVN instructions update the N and Z flags. They have no effect on the C or V flags. NEG instructions update the N, Z, C, and V flags. MOV Rd, Rm behaves as follows: • • if either Rd or Rm is a high register (r8-r15), the flags are unaffected if both Rd and Rm are low registers (r0-r7), the N and Z flags are updated, and C and V flags are cleared.
Thumb Instruction Reference 5.3.5 TST Test bits. Syntax TST Rn, Rm where: Rn is the register containing the first operand. Rm is the register containing the second operand. Usage This instruction performs a bitwise logical AND operation on the values in Rm and Rn. It updates the condition flags, but does not place a result in a register. Restrictions Rn and Rm must be in the range r0-r7. Condition flags This instruction updates the N and Z flags according to the result.
Thumb Instruction Reference 5.4 Thumb branch instructions This section contains the following subsections: • B on page 5-32 Branch. • BL on page 5-34 Branch with Link. • BX on page 5-35 Branch and exchange instruction set. • BLX on page 5-36 Branch with Link and exchange instruction set. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.4.1 B Branch. This is the only instruction in the Thumb instruction set that can be conditional. Syntax B{cond} label where: cond is an optional condition code (see Table 5-2 on page 5-33). label is a program-relative expression. This is usually a label within the same piece of code. See Register-relative and program-relative expressions on page 3-23 for more information.
Thumb Instruction Reference Table 5-2 Condition codes for Thumb B instruction ARM DUI 0068B Suffix Flags Meaning EQ Z set Equal NE Z clear Not equal CS/HS C set Higher or same (unsigned >= ) CC/LO C clear Lower (unsigned < ) MI N set Negative PL N clear Positive or zero VS V set Overflow VC V clear No overflow HI C set and Z clear Higher (unsigned <= ) LS C clear or Z set Lower or same (unsigned <= ) GE N and V the same Signed >= LT N and V different Signed < GT Z
Thumb Instruction Reference 5.4.2 BL Long branch with Link. Syntax BL label where: is a program-relative expression. See Register-relative and program-relative expressions on page 3-23 for more information. label Usage The BL instruction copies the address of the next instruction into r14 (lr, the link register), and causes a branch to label. The machine-level instruction cannot branch to an address outside ±4Mb of the current instruction.
Thumb Instruction Reference 5.4.3 BX Branch, and optionally exchange instruction set. Syntax BX Rm where: is an ARM register containing the address to branch to. Rm Bit 0 of Rm is not used as part of the address. If bit 0 of Rm is clear: • bit 1 must also be clear • the instruction clears the T flag in the CPSR, and the code at the destination is interpreted as ARM code. Usage The BX instruction causes a branch to the address held in Rm, and changes instruction set to Thumb if bit 0 of Rm is set.
Thumb Instruction Reference 5.4.4 BLX Branch with Link, and optionally exchange instruction set. Syntax BLX Rm BLX label where: is an ARM register containing the address to branch to. Rm Bit 0 of Rm is not used as part of the address. If bit 0 of Rm is clear: label • Bit 1 must also be clear. • The instruction clears the T flag in the CPSR. Code at the destination is interpreted as ARM code. is a program-relative expression.
Thumb Instruction Reference 5.5 Thumb software interrupt and breakpoint instructions This section contains the following subsections: • SWI • BKPT on page 5-38. 5.5.1 SWI Software interrupt. Syntax SWI immed_8 where: immed_8 is a numeric expression evaluating to an integer in the range 0-255. Usage The SWI instruction causes a SWI exception.
Thumb Instruction Reference 5.5.2 BKPT Breakpoint. Syntax BKPT immed_8 where: immed_8 is an expression evaluating to an integer in the range 0-255. Usage The BKPT instruction causes the processor to enter Debug mode. Debug tools can use this to investigate system state when the instruction at a particular address is reached. immed_8 is ignored by the processor. However, it is present in bits[7:0] of the instruction opcode.
Thumb Instruction Reference 5.6 Thumb pseudo-instructions The ARM assembler supports a number of Thumb pseudo-instructions that are translated into the appropriate Thumb instructions at assembly time. The pseudo-instructions that are available in Thumb state are in the following sections: • ADR Thumb pseudo-instruction on page 5-40 • LDR Thumb pseudo-instruction on page 5-41 • NOP Thumb pseudo-instruction on page 5-43. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.6.1 ADR Thumb pseudo-instruction The ADR pseudo-instruction loads a program-relative address into a register. Syntax ADR register, expr where: register is the register to load. expr is a program-relative expression. The offset must be positive and less than 1KB. expr must be defined locally, it cannot be imported. Usage In Thumb state, ADR can generate word-aligned addresses only. Use the ALIGN directive to ensure that expr is aligned (see ALIGN on page 7-50).
Thumb Instruction Reference 5.6.2 LDR Thumb pseudo-instruction The LDR pseudo-instruction loads a low register with either: • a 32-bit constant value • an address. Note This section describes the LDR pseudo-instruction only. See Thumb memory access instructions on page 5-4 for information on the LDR instruction. Syntax LDR register, =[expr | label-exp] where: register is the register to be loaded. LDR can access the low registers (r0-r7) only.
Thumb Instruction Reference • To load a program-relative or external address into a register. The address remains valid regardless of where the linker places the ELF section containing the LDR. Example 5-42 LDR r1, =0xfff ; loads 0xfff into r1 LDR r2, =labelname ; loads the address of labelname into r2 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5.6.3 NOP Thumb pseudo-instruction NOP generates the preferred Thumb no-operation instruction. The following instruction might be used, but this is not guaranteed: MOV r8,r8 Syntax The syntax for NOP is: NOP Condition flags ALU status flags are unaltered by NOP. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Thumb Instruction Reference 5-44 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Chapter 6 Vector Floating-point Programming This chapter provides reference information about programming the Vector Floating-point coprocessor in Assembly language.
Vector Floating-point Programming Table 6-1 Location of descriptions of VFP instructions 6-2 Mnemonic Brief description Page Operation Architecture FABS Absolute value page 6-16 Vector All FADD Add page 6-18 Vector All FCMP Compare page 6-19 Scalar All FCPY Copy page 6-16 Vector All FCVTDS Convert single-precision to double-precision page 6-20 Scalar All FCVTSD Convert double-precision to single-precision page 6-21 Scalar All FDIV Divide page 6-22 Vector All FLD L
Vector Floating-point Programming Table 6-1 Location of descriptions of VFP instructions (continued) Mnemonic Brief description Page Operation Architecture FNEG Negate page 6-16 Vector All FNMAC Negate-multiply-accumulate page 6-27 Vector All FNMSC Negate-multiply-subtract page 6-27 Vector All FNMUL Negate-multiply page 6-34 Vector All FSITO Convert signed integer to floating-point page 6-35 Scalar All FSQRT Square Root page 6-36 Vector All FST Store page 6-23 Scalar
Vector Floating-point Programming 6.1 The vector floating-point coprocessor The Vector Floating-Point (VFP) coprocessor, together with associated support code, provides single-precision and double-precision floating-point arithmetic, as defined by ANSI/IEEE Std. 754-1985 IEEE Standard for Binary Floating-Point Arithmetic. This document is referred to as the IEEE 754 standard in this chapter. There is a summary of the standard in the floating-point chapter in ADS Compilers and Libraries Guide.
Vector Floating-point Programming 6.2 Floating-point registers The Vector Floating-point coprocessor has 32 single-precision registers, s0 to s31. Each register can contain either a single-precision floating-point value, or a 32-bit integer. These 32 registers are also treated as 16 double-precision registers, d0 to d15. dn occupies the same hardware as s(2n) and s(2n+1).
Vector Floating-point Programming 6.2.2 Vectors A vector can use up to eight single-precision registers, or four double-precision registers, from the same bank. The number of registers used by a vector is controlled by the LEN bits in the FPSCR (see FPSCR, the floating-point status and control register on page 6-10). A vector can start from any register. The first register used by a vector is specified in the register fields in the individual instructions.
Vector Floating-point Programming 6.3 Vector and scalar operations You can use VFP arithmetic instructions to operate: • on scalars • on vectors • on scalars and vectors together. Use the LEN bits in the FPSCR to control the length of vectors (see FPSCR, the floating-point status and control register on page 6-10). When LEN is 1 all operations are scalar. 6.3.
Vector Floating-point Programming 6.4 VFP and condition codes You can use a condition code to control the execution of any VFP instruction. The instruction is executed conditionally, according to the status flags in the CPSR, in exactly the same way as almost all other ARM instructions. The only VFP instruction that can be used to update the status flags is FCMP.
Vector Floating-point Programming Table 6-2 Condition codes (continued) Mnemonic Meaning after ARM data processing instruction Meaning after VFP FCMP instruction HI Unsigned higher Greater than, or unordered LS Unsigned lower or same Less than or equal GE Signed greater than or equal Greater than or equal LT Signed less than Less than, or unordered GT Signed greater than Greater than LE Signed less than or equal Less than or equal, or unordered AL Always (normally omitted) Always (no
Vector Floating-point Programming 6.5 VFP system registers Three VFP system registers are accessible to you in all implementations of VFP: • FPSCR, the floating-point status and control register • FPEXC, the floating-point exception register on page 6-12 • FPSID, the floating-point system ID register on page 6-12. A particular implementation of VFP can have additional registers (see the technical reference manual for the VFP coprocessor you are using). 6.5.
Vector Floating-point Programming bits[18:16] LEN is the number of registers used by each vector (see Vectors on page 6-6). It is 1 + the value of bits[18:16]: 0b000 LEN = 1 . . 0b111 bits[12:8] LEN = 8. are the exception trap enable bits: IXE inexact exception enable UFE underflow exception enable OFE overflow exception enable DZE division by zero exception enable IOE invalid operation exception enable. This Guide does not cover the use of floating-point exception trapping.
Vector Floating-point Programming 6.5.2 FPEXC, the floating-point exception register You can only access the FPEXC in privileged modes. It contains the following bits: bit[31] is the EX bit. You can read it in all VFP implementations. In some implementations you might also be able to write to it. If the value is 0, the only significant state in the VFP system is the contents of the general purpose registers plus FPSCR and FPEXC.
Vector Floating-point Programming 6.6 Flush-to-zero mode Some implementations of VFP use support code to handle denormalized numbers. The performance of such systems, in calculations involving denormalized numbers, is much less than it is in normal calculations. Flush-to-zero mode replaces denormalized numbers with +0. This does not comply with IEEE 754 arithmetic, but in some circumstances can improve performance considerably. 6.6.
Vector Floating-point Programming 6.6.
Vector Floating-point Programming 6.7 VFP instructions This section contains the following subsections: • FABS, FCPY, and FNEG on page 6-16 Floating-point absolute value, copy, and negate. • FADD and FSUB on page 6-18 Floating-point add and subtract. • FCMP on page 6-19 Floating-point compare. • FCVTDS on page 6-20 Convert single-precision floating-point to double-precision. • FCVTSD on page 6-21 Convert double-precision floating-point to single-precision. • FDIV on page 6-22 Floating-point divide.
Vector Floating-point Programming 6.7.1 FABS, FCPY, and FNEG Floating-point copy, absolute value, and negate. These instructions can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax {cond} Fd, Fm where: must be one of FCPY, FABS, or FNEG. must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register for the result.
Vector Floating-point Programming Examples FABSD d3, d5 FNEGSMI s15, s15 ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Vector Floating-point Programming 6.7.2 FADD and FSUB Floating-point add and subtract. FADD and FSUB can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax FADD{cond} Fd, Fn, Fm FSUB{cond} Fd, Fn, Fm where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register for the result.
Vector Floating-point Programming 6.7.3 FCMP Floating-point compare. FCMP is always scalar. Syntax FCMP{E}{cond} Fd, Fm FCMP{E}Z{cond} Fd where: E is an optional parameter. If E is present, an exception is raised if either operand is any kind of NaN. Otherwise, an exception is raised only if either operand is a signalling NaN. Z is a parameter specifying comparison with zero. must be either S for single-precision, or D for double-precision.
Vector Floating-point Programming 6.7.4 FCVTDS Convert single-precision floating-point to double-precision. FCVTDS is always scalar. Syntax FCVTDS{cond} Dd, Sm where: cond is an optional condition code (see VFP and condition codes on page 6-8). Dd is a double-precision VFP register for the result. Sm is a single-precision VFP register holding the operand. Usage The FCVTDS instruction converts the single-precision value in Sm to double-precision and places the result in Dd.
Vector Floating-point Programming 6.7.5 FCVTSD Convert double-precision floating-point to single-precision. FCVTSD is always scalar. Syntax FCVTSD{cond} Sd, Dm where: cond is an optional condition code (see VFP and condition codes on page 6-8). Sd is a single-precision VFP register for the result. Dm is a double-precision VFP register holding the operand. Usage The FCVTSD instruction converts the double-precision value in Dm to single-precision and places the result in Sd.
Vector Floating-point Programming 6.7.6 FDIV Floating-point divide. FDIV can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax FDIV{cond} Fd, Fn, Fm where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register for the result. Fn is the VFP register holding the first operand. Fm is the VFP register holding the second operand.
Vector Floating-point Programming 6.7.7 FLD and FST Floating-point load and store. Syntax FLD{cond} Fd, [Rn{, #offset}] FST{cond} Fd, [Rn{, #offset}] FLD{cond} Fd, label FST{cond} Fd, label where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register to be loaded or saved.
Vector Floating-point Programming FLDSNE FSTS FLDD FLDS 6-24 s3, s2, d2, s9, [r2, #72+count] [r5] [r15, #addr-{PC}] fpconst Copyright © 2000, 2001 ARM Limited. All rights reserved.
Vector Floating-point Programming 6.7.8 FLDM and FSTM Floating-point load multiple and store multiple. Syntax FLDM{cond} Rn,{!} VFPregisters FSTM{cond} Rn,{!} VFPregisters where: must be one of: IA meaning Increment address After each transfer. DB meaning Decrement address Before each transfer. EA meaning Empty Ascending stack operation. This is the same as DB for loads, and the same as IA for saves.
Vector Floating-point Programming Usage The FLDM instruction loads several consecutive floating-point registers from memory. The FSTM instruction saves the contents of several consecutive floating-point registers to memory. If is specified as D, VFPregisters must be a list of double-precision registers, and two words are transferred for each register in the list.
Vector Floating-point Programming 6.7.9 FMAC, FNMAC, FMSC, and FNMSC Floating-point multiply-accumulate, negate-multiply-accumulate, multiply-subtract and negate-multiply-subtract. These instructions can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax {cond} Fd, Fn, Fm where: must be one of FMAC, FNMAC, FMSC, or FNMSC. must be either S for single-precision, or D for double-precision.
Vector Floating-point Programming FNMSCSLE 6-28 s6, s0, s26 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Vector Floating-point Programming 6.7.10 FMDRR and FMRRD Transfer contents between two ARM registers and a double-precision floating-point register. Syntax FMDRR{cond} Dn, Rd, Rn FMRRD{cond} Rd, Rn, Dn where: cond is an optional condition code (see VFP and condition codes on page 6-8). Dn is the VFP double-precision register. Rd, Rn are ARM registers. Do not use r15. Usage FMDRR Dn, Rd, Rn transfers the contents of Rd into the low half of Dn, and the contents of Rn into the high half of Dn.
Vector Floating-point Programming 6.7.11 FMDHR, FMDLR, FMRDH, and FMRDL Transfer contents between an ARM register and a half of a double-precision floating-point register. Syntax FMDHR{cond} Dn, Rd FMDLR{cond} Dn, Rd FMRDH{cond} Rd, Dn FMRDL{cond} Rd, Dn where: cond is an optional condition code (see VFP and condition codes on page 6-8). Dn is the VFP double-precision register. Rd is the ARM register. Rd must not be r15.
Vector Floating-point Programming 6.7.12 FMRS and FMSR Transfer contents between a single-precision floating-point register and an ARM register. Syntax FMRS{cond} Rd, Sn FMSR{cond} Sn, Rd where: cond is an optional condition code (see VFP and condition codes on page 6-8). Sn is the VFP single-precision register. Rd is the ARM register. Rd must not be r15. Usage The FMRS instruction transfers the contents of Sn into Rd. The FMSR instruction transfers the contents of Rd into Sn.
Vector Floating-point Programming 6.7.13 FMRRS and FMSRR Transfer contents between two single-precision floating-point registers and two ARM registers. Syntax FMRRS{cond} Rd, Rn, {Sn,Sm} FMSRR{cond} {Sn,Sm}, Rd, Rn where: cond is an optional condition code (see VFP and condition codes on page 6-8). Sn, Sm are two consecutive VFP single-precision registers. Rd, Rn are the ARM registers. Do not use r15. Usage The FMRRS instruction transfers the contents of Sn into Rd, and the contents of Sm into Rn.
Vector Floating-point Programming 6.7.14 FMRX, FMXR, and FMSTAT Transfer contents between an ARM register and a VFP system register. Syntax FMRX{cond} Rd, VFPsysreg FMXR{cond} VFPsysreg, Rd FMSTAT{cond} where: cond is an optional condition code (see VFP and condition codes on page 6-8). VFPsysreg is the VFP system register, usually FPSCR, FPSID, or FPEXC (see Floating-point registers on page 6-5). Rd is the ARM register. Usage The FMRX instruction transfers the contents of VFPsysreg into Rd.
Vector Floating-point Programming 6.7.15 FMUL and FNMUL Floating-point multiply and negate-multiply. FMUL and FNMUL can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax FMUL{cond} Fd, Fn, Fm FNMUL{cond} Fd, Fn, Fm where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register for the result.
Vector Floating-point Programming 6.7.16 FSITO and FUITO Convert signed integer to floating-point and unsigned integer to floating-point. FSITO and FUITO are always scalar. Syntax FSITO{cond} Fd, Sm FUITO{cond} Fd, Sm where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is a VFP register for the result.
Vector Floating-point Programming 6.7.17 FSQRT Floating-point square root instruction. This instruction can be scalar, vector, or mixed (see Vector and scalar operations on page 6-7). Syntax FSQRT{cond} Fd, Fm where: must be either S for single-precision, or D for double-precision. cond is an optional condition code (see VFP and condition codes on page 6-8). Fd is the VFP register for the result. Fm is the VFP register holding the operand.
Vector Floating-point Programming 6.7.18 FTOSI and FTOUI Convert floating-point to signed integer and floating-point to unsigned integer. FTOSI and FTOUI are always scalar. Syntax FTOSI{Z}{cond} Sd, Fm FTOUI{Z}{cond} Sd, Fm where: is an optional parameter specifying rounding towards zero. If specified, this overrides the rounding mode currently specified in the FPSCR. The FPSCR is not altered. Z must be either S for single-precision, or D for double-precision.
Vector Floating-point Programming 6.8 VFP pseudo-instruction There is one VFP pseudo-instruction. 6.8.1 FLD pseudo-instruction The FLD pseudo-instruction loads a VFP floating-point register with a single-precision or double-precision floating-point constant. Note You can use FLD only if the command line option -fpu is set to vfp or softvfp+vfp. This section describes the FLD pseudo-instruction only. See FLD and FST on page 6-23 for information on the FLD instruction.
Vector Floating-point Programming Examples FLDD FLDS ARM DUI 0068B d1,=3.12E106 s31,=3.12E-16 ; loads 3.12E106 into d1 ; loads 3.12E-16 into s31 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Vector Floating-point Programming 6.9 VFP directives and vector notation This section applies only to armasm. The inline assemblers in the C and C++ compilers do not accept these directives or vector notation. You can make assertions about VFP vector lengths and strides in your code, and have them checked by the assembler. See: • VFPASSERT SCALAR on page 6-41 • VFPASSERT VECTOR on page 6-42. If you use VFPASSERT directives, you must specify vector details in all VFP data processing instructions.
Vector Floating-point Programming 6.9.1 VFPASSERT SCALAR The VFPASSERT SCALAR directive informs the assembler that following VFP instructions are in scalar mode. Syntax VFPASSERT SCALAR Usage Use the VFPASSERT SCALAR directive to mark the end of any block of code where the VFP mode is VECTOR. Place the VFPASSERT SCALAR directive immediately after the instruction where the change occurs. This is usually an FMXR instruction, but might be a BL instruction.
Vector Floating-point Programming 6.9.2 VFPASSERT VECTOR The VFPASSERT VECTOR directive informs the assembler that following VFP instructions are in vector mode. It can also specify the length and stride of the vectors. Syntax VFPASSERT VECTOR[<[n[:s]]>] where: n is the vector length, 1-8. s is the vector stride, 1-2. Usage Use the VFPASSERT VECTOR directive to mark the start of a block of instructions where the VFP mode is VECTOR, and to mark changes in the length or stride of vectors.
Vector Floating-point Programming Example FMRX BIC ORR FMXR r10,FPSCR r10,r10,#0x00370000 r10,r10,#0x00020000 FPSCR,r10 VFPASSERT VECTOR faddd d4, d4, d0 fadds s16<3>, s0, s8<3> fabss s24<1>, s28<1> ; set length = 3, stride = 1 FMRX BIC ORR FMXR ; ; ; ; r10,FPSCR r10,r10,#0x00370000 r10,r10,#0x00030000 FPSCR,r10 ; set length = 4, stride = 1 VFPASSERT VECTOR<4> fadds s24<4>, s0, s8<4> fabss s24<2>, s24<2> FMRX BIC ORR FMXR ; assert vector mode, length 4, stride 1 ; okay ; ERROR, wrong length r10,F
Vector Floating-point Programming 6-44 Copyright © 2000, 2001 ARM Limited. All rights reserved.
Chapter 7 Directives Reference This chapter describes the directives that are provided by the ARM assembler, armasm. It contains the following sections: • Alphabetical list of directives on page 7-2 • Symbol definition directives on page 7-3 • Data definition directives on page 7-13 Allocate memory, define data structures, set initial contents of memory. • Assembly control directives on page 7-26 Conditional assembly, looping, inclusions, and macros.
Directives Reference 7.
Directives Reference 7.2 Symbol definition directives This section describes the following directives: • GBLA, GBLL, and GBLS on page 7-4 Declare a global arithmetic, logical, or string variable. • LCLA, LCLL, and LCLS on page 7-6 Declare a local arithmetic, logical, or string variable. • SETA, SETL, and SETS on page 7-7 Set the value of an arithmetic, logical, or string variable. • RLIST on page 7-8 Define a name for a set of general-purpose registers.
Directives Reference 7.2.1 GBLA, GBLL, and GBLS The GBLA directive declares a global arithmetic variable, and initializes its value to 0. The GBLL directive declares a global logical variable, and initializes its value to {FALSE}. The GBLS directive declares a global string variable and initializes its value to a null string, "". Syntax variable where: is one of GBLA, GBLL, or GBLS. variable is the name of the variable. variable must be unique amongst symbols within a source file.
Directives Reference Examples Example 7-1 declares a variable objectsize, sets the value of objectsize to 0xFF, and then uses it later in a SPACE directive. Example 7-1 objectsize GBLA SETA . . . SPACE objectsize 0xFF ; declare the variable name ; set its value ; other code objectsize ; quote the variable Example 7-2 shows how to declare and set a variable when you invoke armasm. Use this when you need to set the value of a variable at assembly time. -pd is a synonym for -predefine.
Directives Reference 7.2.2 LCLA, LCLL, and LCLS The LCLA directive declares a local arithmetic variable, and initializes its value to 0. The LCLL directive declares a local logical variable, and initializes its value to {FALSE}. The LCLS directive declares a local string variable, and initializes its value to a null string, "". Syntax variable where: is one of LCLA, LCLL, or LCLS. is the name of the variable. variable must be unique within the macro that contains it.
Directives Reference 7.2.3 SETA, SETL, and SETS The SETA directive sets the value of a local or global arithmetic variable. The SETL directive sets the value of a local or global logical variable. The SETS directive sets the value of a local or global string variable. Syntax variable expr where: is one of SETA, SETL, or SETS. variable is the name of a variable declared by a GBLA, GBLL, GBLS, LCLA, LCLL, or LCLS directive.
Directives Reference 7.2.4 RLIST The RLIST (register list) directive gives a name to a set of general-purpose registers. Syntax name RLIST {list-of-registers} where: is the name to be given to the set of registers. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9. name list-of-registers is a comma-delimited list of register names and/or register ranges. The register list must be enclosed in braces.
Directives Reference 7.2.5 CN The CN directive defines a name for a coprocessor register. Syntax name CN expr where: name is the name to be defined for the coprocessor register. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9. expr evaluates to a coprocessor register number from 0 to 15. Usage Use CN to allocate convenient names to registers, to help you remember what you use each register for.
Directives Reference 7.2.6 CP The CP directive defines a name for a specified coprocessor. The coprocessor number must be within the range 0 to 15. Syntax name CP expr where: name is the name to be assigned to the coprocessor. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9. expr evaluates to a coprocessor number from 0 to 15.
Directives Reference 7.2.7 DN and SN The DN directive defines a name for a specified double-precision VFP register. The names d0-d15 and D0-D15 are predefined. The SN directive defines a name for a specified single-precision VFP register. The names s0-s31 and S0-S31 are predefined. Syntax name DN expr name SN expr where: name is the name to be assigned to the VFP register. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9.
Directives Reference 7.2.8 FN The FN directive defines a name for a specified FPA floating-point register. The names f0-f7 and F0-F7 are predefined. Syntax name FN expr where: name is the name to be assigned to the floating-point register. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9. expr evaluates to a floating-point register number from 0 to 7.
Directives Reference 7.3 Data definition directives This section describes the following directives: • LTORG on page 7-14 Set an origin for a literal pool. • MAP on page 7-15 Set the origin of a storage map. • FIELD on page 7-16 Define a field within a storage map. • SPACE on page 7-17 Allocate a zeroed block of memory. • DCB on page 7-18 Allocate bytes of memory, and specify the initial contents. • DCD and DCDU on page 7-19 Allocate words of memory, and specify the initial contents.
Directives Reference 7.3.1 LTORG The LTORG directive instructs the assembler to assemble the current literal pool immediately. Syntax LTORG Usage The assembler assembles the current literal pool at the end of every code section. The end of a code section is determined by the AREA directive at the beginning of the following section, or the end of the assembly. These default literal pools can sometimes be out of range of some LDR, LDFD, and LDFS pseudo-instructions.
Directives Reference 7.3.2 MAP The MAP directive sets the origin of a storage map to a specified address. The storage-map location counter, {VAR}, is set to the same address. ^ is a synonym for MAP. Syntax MAP expr{,base-register} where: is a numeric or program-relative expression: expr • If base-register is not specified, expr evaluates to the address where the storage map starts. The storage map location counter is set to this address.
Directives Reference 7.3.3 FIELD The FIELD directive describes space within a storage map that has been defined using the MAP directive. # is a synonym for FIELD. Syntax {label} FIELD expr where: label is an optional label. If specified, label is assigned the value of the storage location counter, {VAR}. The storage location counter is then incremented by the value of expr. expr is an expression that evaluates to the number of bytes to increment the storage counter.
Directives Reference 7.3.4 SPACE The SPACE directive reserves a zeroed block of memory. % is a synonym for SPACE. Syntax {label} SPACE expr where: evaluates to the number of zeroed bytes to reserve (see Numeric expressions on page 3-20). expr Usage You must use a DATA directive if you use SPACE to define labeled data within Thumb code. See DATA on page 7-25 for more information. Use the ALIGN directive to align any code following a SPACE directive. See ALIGN on page 7-50 for more information.
Directives Reference 7.3.5 DCB The DCB directive allocates one or more bytes of memory, and defines the initial runtime contents of the memory. = is a synonym for DCB. Syntax {label} DCB expr{,expr}... where: is either: • A numeric expression that evaluates to an integer in the range –128 to 255 (see Numeric expressions on page 3-20). • A quoted string. The characters of the string are loaded into consecutive bytes of store.
Directives Reference 7.3.6 DCD and DCDU The DCD directive allocates one or more words of memory, aligned on 4-byte boundaries, and defines the initial runtime contents of the memory. & is a synonym for DCD. DCDU is the same, except that the memory alignment is arbitrary. Syntax {label} DCD{U} expr{,expr} where: is either: • a numeric expression (see Numeric expressions on page 3-20). • a program-relative expression.
Directives Reference 7.3.7 DCDO The DCDO directive allocates one or more words of memory, aligned on 4-byte boundaries, and defines the initial runtime contents of the memory as an offset from the static base register, sb (r9). Syntax {label} DCDO expr{,expr}... where: is a register-relative expression or label. The base register must be sb. expr Usage Use DCDO to allocate space in memory for static base register relative relocatable addresses.
Directives Reference 7.3.8 DCFD and DCFDU The DCFD directive allocates memory for word-aligned double-precision floating-point numbers, and defines the initial runtime contents of the memory. Double-precision numbers occupy two words and must be word aligned to be used in arithmetic operations. DCDFU is the same, except that the memory alignment is arbitrary. Syntax {label} DCFD{U} fpliteral{,fpliteral}...
Directives Reference 7.3.9 DCFS and DCFSU The DCFS directive allocates memory for word-aligned single-precision floating-point numbers, and defines the initial runtime contents of the memory. Single-precision numbers occupy one word and must be word aligned to be used in arithmetic operations. DCDSU is the same, except that the memory alignment is arbitrary. Syntax {label} DCFS{U} fpliteral{,fpliteral}...
Directives Reference 7.3.10 DCI In ARM code, the DCI directive allocates one or more words of memory, aligned on 4-byte boundaries, and defines the initial runtime contents of the memory. In Thumb code, the DCI directive allocates one or more halfwords of memory, aligned on 2-byte boundaries, and defines the initial runtime contents of the memory. Syntax {label} DCI expr{,expr} where: is a numeric expression (see Numeric expressions on page 3-20).
Directives Reference 7.3.11 DCQ and DCQU The DCQ directive allocates one or more 8-byte blocks of memory, aligned on 4-byte boundaries, and defines the initial runtime contents of the memory. DCQU is the same, except that the memory alignment is arbitrary. Syntax {label} DCQ{U} {-}literal{,{-}literal}... where: is a 64-bit numeric literal (see Numeric literals on page 3-21). literal The range of numbers allowed is 0 to 264 – 1.
Directives Reference 7.3.12 DCW and DCWU The DCW directive allocates one or more halfwords of memory, aligned on 2-byte boundaries, and defines the initial runtime contents of the memory. DCWU is the same, except that the memory alignment is arbitrary. Syntax {label} DCW expr{,expr}... where: is a numeric expression that evaluates to an integer in the range –32768 to 65535 (see Numeric expressions on page 3-20).
Directives Reference 7.4 Assembly control directives This section describes the following directives: • MACRO and MEND on page 7-27 • MEXIT on page 7-29 • IF, ELSE, and ENDIF on page 7-30 • WHILE and WEND on page 7-32. 7.4.1 Nesting directives The following structures can be nested to a total depth of 256: • MACRO definitions • WHILE...WEND loops • IF...ELSE...ENDIF conditional structures • INCLUDE file inclusions. The limit applies to all structures taken together, however they are nested.
Directives Reference 7.4.2 MACRO and MEND The MACRO directive marks the start of the definition of a macro. Macro expansion terminates at the MEND directive. See Using macros on page 2-48 for further information. Syntax Two directives are used to define a macro. The syntax is: {$label} MACRO macroname {$parameter{,$parameter}...} ; code MEND where: $label is a parameter that is substituted with a symbol given when the macro is invoked. The symbol is usually a label. macroname is the name of the macro.
Directives Reference Use | as the argument to use the default value of a parameter. An empty string is used if the argument is omitted. In a macro that uses several internal labels, it is useful to define each internal label as the base label with a different suffix. Use a dot between a parameter and following text, or a following parameter, if a space is not required in the expansion. Do not use a dot between preceding text and a parameter.
Directives Reference Using a macro to produce assembly-time diagnostics: MACRO diagnose INFO MEND $param1="default" 0,"$param1" ; ; ; ; Macro definition This macro produces assembly-time diagnostics (on second assembly pass) ; macro expansion diagnose diagnose "hello" diagnose | 7.4.3 ; Prints blank line at assembly-time ; Prints "hello" at assembly-time ; Prints "default" at assembly-time MEXIT The MEXIT directive is used to exit a macro definition before the end.
Directives Reference 7.4.4 IF, ELSE, and ENDIF The IF directive introduces a condition that is used to decide whether to assemble a sequence of instructions and/or directives. [ is a synonym for IF. The ELSE directive marks the beginning of a sequence of instructions and/or directives that you want to be assembled if the preceding condition fails. | is a synonym for ELSE. The ENDIF directive marks the end of a sequence of instructions and/or directives that you want to be conditionally assembled.
Directives Reference Examples Example 7-3 assembles the first set of instructions if NEWVERSION is defined, or the alternative set otherwise. Example 7-3 Assembly conditional on a variable being defined IF :DEF:NEWVERSION ; first set of instructions/directives ELSE ; alternative set of instructions/directives ENDIF Invoking armasm as follows defines NEWVERSION, so the first set of instructions and directives are assembled: armasm -PD "NEWVERSION SETL {TRUE}" test.
Directives Reference 7.4.5 WHILE and WEND The WHILE directive starts a sequence of instructions or directives that are to be assembled repeatedly. The sequence is terminated with a WEND directive. Syntax WHILE logical-expression code WEND where: logical-expression is an expression that can evaluate to either {TRUE} or {FALSE} (see Logical expressions on page 3-23). Usage Use the WHILE directive, together with the WEND directive, to assemble a sequence of instructions a number of times.
Directives Reference 7.5 Frame description directives This section describes the following directives: • FRAME ADDRESS on page 7-34 • FRAME POP on page 7-35 • FRAME PUSH on page 7-36 • FRAME REGISTER on page 7-37 • FRAME RESTORE on page 7-38 • FRAME SAVE on page 7-39 • FRAME STATE REMEMBER on page 7-40 • FRAME STATE RESTORE on page 7-41 • FUNCTION or PROC on page 7-42 • ENDFUNC or ENDP on page 7-43.
Directives Reference 7.5.1 FRAME ADDRESS The FRAME ADDRESS directive describes how to calculate the canonical frame address for following instructions. You can only use it in functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax FRAME ADDRESS reg[,offset] where: reg is the register on which the canonical frame address is to be based. This is sp unless the function uses a separate frame pointer. offset is the offset of the canonical frame address from reg.
Directives Reference 7.5.2 FRAME POP Use the FRAME POP directive to inform the assembler when the callee reloads registers. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. You need not do this after the last instruction in a function. Syntax There are two alternative syntaxes for FRAME POP: FRAME POP {reglist} FRAME POP n where: reglist is a list of registers restored to the values they had on entry to the function.
Directives Reference 7.5.3 FRAME PUSH Use the FRAME PUSH directive to inform the assembler when the callee saves registers, normally at function entry. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax There are two alternative syntaxes for FRAME PUSH: FRAME PUSH {reglist} FRAME PUSH n where: reglist is a list of registers stored consecutively below the canonical frame address. There must be at least one register in the list.
Directives Reference Example p 7.5.4 PROC ; Canonical frame address is sp + 0 EXPORT p STMFD sp!,{r4-r6,lr} ; sp has moved relative to the canonical frame address, ; and registers r4, r5, r6 and lr are now on the stack FRAME PUSH {r4-r6,lr} ; Equivalent to: ; FRAME ADDRESS sp,16 ; 16 bytes in {r4-r6,lr} ; FRAME SAVE {r4-r6,lr},-16 FRAME REGISTER Use the FRAME REGISTER directive to maintain a record of the locations of function arguments held in registers.
Directives Reference 7.5.5 FRAME RESTORE Use the FRAME RESTORE directive to inform the assembler that the contents of specified registers have been restored to the values they had on entry to the function. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax FRAME RESTORE {reglist} where: reglist is a list of registers whose contents have been restored. There must be at least one register in the list.
Directives Reference 7.5.6 FRAME SAVE The FRAME SAVE directive describes the location of saved register contents relative to the canonical frame address. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax FRAME SAVE {reglist}, offset where: reglist is a list of registers stored consecutively starting at offset from the canonical frame address. There must be at least one register in the list.
Directives Reference 7.5.7 FRAME STATE REMEMBER The FRAME STATE REMEMBER directive saves the current information on how to calculate the canonical frame address and locations of saved register values. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax FRAME STATE REMEMBER Usage During an inline exit sequence the information about calculation of canonical frame address and locations of saved register values can change.
Directives Reference 7.5.8 FRAME STATE RESTORE The FRAME STATE RESTORE directive restores information about how to calculate the canonical frame address and locations of saved register values. You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives. Syntax FRAME STATE RESTORE Usage See: • FRAME STATE REMEMBER on page 7-40 • FUNCTION or PROC on page 7-42. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Directives Reference 7.5.9 FUNCTION or PROC The FUNCTION directive marks the start of an ATPCS-conforming function. PROC is a synonym for FUNCTION. Syntax label FUNCTION Usage Use FUNCTION to mark the start of functions. The assembler uses FUNCTION to identify the start of a function when producing DWARF call frame information for ELF. FUNCTION sets the canonical frame address to be sp, and the frame state stack to be empty. Each FUNCTION directive must have a matching ENDFUNC directive.
Directives Reference 7.5.10 ENDFUNC or ENDP The ENDFUNC directive marks the end of an ATPCS-conforming function (see FUNCTION or PROC on page 7-42). ENDP is a synonym for ENDFUNC. ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved.
Directives Reference 7.6 Reporting directives This section describes the following directives: • ASSERT generates an error message if an assertion is false during assembly. • INFO on page 7-45 generates diagnostic information during assembly. • OPT on page 7-46 sets listing options. • TTL and SUBT on page 7-48 insert titles and subtitles in listings. 7.6.1 ASSERT The ASSERT directive generates an error message during the second pass of the assembly if a given assertion is false.
Directives Reference 7.6.2 INFO The INFO directive supports diagnostic generation on either pass of the assembly. ! is very similar to INFO, but has less detailed reporting. Syntax INFO numeric-expression, string-expression where: numeric-expression is a numeric expression that is evaluated during assembly. If the expression evaluates to zero: • no action is taken during pass one • string-expression is printed during pass two.
Directives Reference 7.6.3 OPT The OPT directive sets listing options from within the source code. Syntax OPT n where: is the OPT directive setting. Table 7-2 lists valid settings. n Table 7-2 OPT directive settings OPT n Effect 1 Turns on normal listing. 2 Turns off normal listing. 4 Page throw. Issues an immediate form feed and starts a new page. 8 Resets the line number counter to zero. 16 Turns on listing for SET, GBL and LCL directives.
Directives Reference By default the -list option produces a normal listing that includes variable declarations, macro expansions, call-conditioned directives, and MEND directives. The listing is produced on the second pass only. Use the OPT directive to modify the default listing options from within your code. See Command syntax on page 3-2 for information on the -list option. You can use OPT to format code listings. For example, you can specify a new page before functions and sections.
Directives Reference 7.6.4 TTL and SUBT The TTL directive inserts a title at the start of each page of a listing file. The title is printed on each page until a new TTL directive is issued. The SUBT directive places a subtitle on the pages of a listing file. The subtitle is printed on each page until a new SUBT directive is issued. Syntax TTL title SUBT subtitle where: title is the title subtitle is the subtitle. Usage Use the TTL directive to place a title at the top of the pages of a listing file.
Directives Reference 7.
Directives Reference 7.7.1 ALIGN The ALIGN directive aligns the current location to a specified boundary by padding with zeroes. Syntax ALIGN {expr{,offset}} where: expr is a numeric expression evaluating to any power of 2 from 20 to 231. offset can be any numeric expression. The current location is aligned to the next address of the form: offset + n * expr If expr is not specified, ALIGN sets the current location to the next word (four byte) boundary.
Directives Reference Examples rout1 rout2 AREA ; code ; code MOV ALIGN ; code cacheable, CODE, ALIGN=3 ; aligned on 8-byte boundary AREA DCB ALIGN DCB OffsetExample, CODE 1 ; This example places the two 4,3 ; bytes in the first and fourth 1 ; bytes of the same word.
Directives Reference 7.7.2 AREA The AREA directive instructs the assembler to assemble a new code or data section. Sections are independent, named, indivisible chunks of code or data that are manipulated by the linker. See ELF sections and the AREA directive on page 2-15 for more information. Syntax AREA sectionname{,attr}{,attr}... where: sectionname is the name that the section is to be given. You can choose any name for your sections.
Directives Reference Identical ELF sections with the same name are overlaid in the same section of memory by the linker. If any are different, the linker generates a warning and does not overlay the sections. See the Linker chapter in ADS Linker and Utilities Guide. COMMON Is a common data section. You must not define any code or data in it. It is initialized to zeroes by the linker. All common sections with the same name are overlaid in the same section of memory by the linker.
Directives Reference 7.7.3 CODE16 and CODE32 The CODE16 directive instructs the assembler to interpret subsequent instructions as 16-bit Thumb instructions. If necessary, it also inserts a byte of padding to align to the next halfword boundary. The CODE32 directive instructs the assembler to interpret subsequent instructions as 32-bit ARM instructions. If necessary, it also inserts up to three bytes of padding to align to the next word boundary.
Directives Reference 7.7.4 END The END directive informs the assembler that it has reached the end of a source file. Syntax END Usage Every assembly language source file must end with END on a line by itself. If the source file has been included in a parent file by a GET directive, the assembler returns to the parent file and continues assembly at the first line following the GET directive. See GET or INCLUDE on page 7-61 for more information.
Directives Reference 7.7.5 ENTRY The ENTRY directive declares an entry point to a program. Syntax ENTRY Usage You must specify at least one ENTRY point for a program. If no ENTRY exists, a warning is generated at link time. You must not use more than one ENTRY directive in a single source file. Not every source file has to have an ENTRY directive. If more than one ENTRY exists in a single source file, an error message is generated at assembly time.
Directives Reference 7.7.6 EQU The EQU directive gives a symbolic name to a numeric constant, a register-relative value or a program-relative value. * is a synonym for EQU. Syntax name EQU expr{, type} where: name is the symbolic name to assign to the value. expr is a register-relative address, a program-relative address, an absolute address, or a 32-bit integer constant. type is optional. type can be any one of: • CODE16 • CODE32 • DATA You can use type only if expr is an absolute address.
Directives Reference 7.7.7 EXPORT or GLOBAL The EXPORT directive declares a symbol that can be used by the linker to resolve symbol references in separate object and library files. GLOBAL is a synonym for EXPORT. Syntax EXPORT {symbol}{[WEAK]} where: symbol is the symbol name to export. The symbol name is case-sensitive. If symbol is omitted, all symbols are exported.
Directives Reference 7.7.8 EXPORTAS The EXPORTAS directive allows you to export a symbol to the object file, corresponding to a different symbol in the source file. Syntax EXPORTAS symbol1, symbol2 where: symbol1 is the symbol name in the source file. symbol1 must have been defined already. It can be any symbol, including an area name, a label, or a constant. symbol2 is the symbol name you want to appear in the object file. The symbol names are case-sensitive.
Directives Reference 7.7.9 EXTERN The EXTERN directive provides the assembler with a name that is not defined in the current assembly. EXTERN is very similar to IMPORT, except that the name is not imported if no reference to it is found in the current assembly (see IMPORT on page 7-62, and EXPORT or GLOBAL on page 7-58). Syntax EXTERN symbol{[WEAK]} where: symbol is a symbol name defined in a separately assembled source file, object file, or library. The symbol name is case-sensitive.
Directives Reference 7.7.10 GET or INCLUDE The GET directive includes a file within the file being assembled. The included file is assembled at the location of the GET directive. INCLUDE is a synonym for GET. Syntax GET filename where: filename is the name of the file to be included in the assembly. The assembler accepts pathnames in either UNIX or MS-DOS format. Usage GET is useful for including macro definitions, EQUs, and storage maps in an assembly.
Directives Reference 7.7.11 GLOBAL See EXPORT or GLOBAL on page 7-58. 7.7.12 IMPORT The IMPORT directive provides the assembler with a name that is not defined in the current assembly. IMPORT is very similar to EXTERN, except that the name is imported whether or not it is referred to in the current assembly (see EXTERN on page 7-60, and EXPORT or GLOBAL on page 7-58). Syntax IMPORT symbol{[WEAK]} where: symbol is a symbol name defined in a separately assembled source file, object file, or library.
Directives Reference 7.7.13 INCBIN The INCBIN directive includes a file within the file being assembled. The file is included as it is, without being assembled. Syntax INCBIN filename where: is the name of the file to be included in the assembly. The assembler accepts pathnames in either UNIX or MS-DOS format. filename Usage You can use INCBIN to include executable files, literals, or any arbitrary data.
Directives Reference 7.7.15 KEEP The KEEP directive instructs the assembler to retain local symbols in the symbol table in the object file. Syntax KEEP {symbol} where: is the name of the local symbol to keep. If symbol is not specified, all local symbols are kept except register-relative symbols. symbol Usage By default, the only symbols that the assembler describes in its output object file are: • exported symbols • symbols that are relocated against.
Directives Reference 7.7.16 NOFP The NOFP directive disallows floating-point instructions in an assembly language source file. Syntax NOFP Usage Use NOFP to ensure that no floating-point instructions are used in situations where there is no support for floating-point instructions either in software or in target hardware. If a floating-point instruction occurs after the NOFP directive, an Unknown opcode error is generated and the assembly fails.
Directives Reference 7.7.18 REQUIRE8 and PRESERVE8 The REQUIRE8 directive specifies that the current file requires 8-byte alignment of the stack. The PRESERVE8 directive specifies that the current file preserves 8-byte alignment of the stack. Syntax REQUIRE8 PRESERVE8 Usage LDRD and STRD instructions (double-word transfers) only work correctly if the address they access is 8-byte aligned.
Directives Reference 7.7.19 RN The RN directive defines a register name for a specified register. Syntax name RN expr where: name is the name to be assigned to the register. name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3-9. expr evaluates to a register number from 0 to 15. Usage Use RN to allocate convenient names to registers, to help you to remember what you use each register for.
Directives Reference 7.7.20 ROUT The ROUT directive marks the boundaries of the scope of local labels (see Local labels on page 3-16). Syntax {name} ROUT where: is the name to be assigned to the scope. name Usage Use the ROUT directive to limit the scope of local labels. This makes it easier for you to avoid referring to a wrong label by accident. The scope of local labels is the whole area if there are no ROUT directives in it (see AREA on page 7-52).
Glossary ADS See ARM Developer Suite. ANSI American National Standards Institute. An organization that specifies standards for, among other things, computer software. Angel™ Angel is a program that enables you to develop and debug applications running on ARM-based hardware. Angel can debug applications running in either ARM state or Thumb state. Architecture The term used to identify a group of processors that have similar characteristics.
Glossary ATPCS ARM and Thumb Procedure Call Standard defines how registers and the stack will be used for subroutine calls. AXD See ARM eXtended Debugger. Big-endian Memory organization where the least significant byte of a word is at a higher address than the most significant byte. Byte A unit of memory storage consisting of eight bits. Canonical Frame Address In DWARF 2, this is an address on the stack specifying where the call frame of an interrupted function is located.
Glossary Interrupt A change in the normal processing sequence of an application caused by, for example, an external signal. Interworking Producing an application that uses both ARM and Thumb code. Library A collection of assembler or compiler output objects grouped together into a single repository. Linker Software which produces a single image from one or more source assembler or compiler output objects.
Glossary Scope The accessibility of a function or variable at a particular point in the application code. Symbols which have global scope are always accessible. Symbols with local or private scope are only accessible to code in the same subroutine or object. Section A block of software code or data for an Image. Semihosting A mechanism whereby the target communicates I/O requests made in the application code to the host system, rather attempting to support the I/O itself.
Index The items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The references given are to page numbers.
Index numeric expressions 3-20 numeric literals 3-21 numeric variables 3-13 operator precedence 3-24, 3-25 padding 2-56 pc 2-5, 2-40, 2-43, 2-46, 3-10, 3-15, 3-23 program counter 2-5, 3-10, 3-15, 3-23 program-relative 2-13 expressions 3-23 program-relative labels 3-15 program-relative maps 2-54 register names 3-9 register-based maps 2-53 register-relative expressions 3-23 labels 3-15 register-relative address 2-13 relational operators 3-30 relative maps 2-52 shift operators 3-29 speed 2-61 stacks 2-42 stri
Index GBLA 3-6, 3-13, 7-4, 7-46 GBLL 3-6, 3-13, 7-4, 7-46 GBLS 3-6, 3-13, 7-4, 7-46 GET 3-5, 7-61 GLOBAL 7-58, 7-59 IF 7-29, 7-30, 7-32 IMPORT 7-62 INCBIN 7-63 INCLUDE 3-5, 7-61 INFO 7-45 KEEP 7-64 LCLA 3-13, 7-6, 7-46 LCLL 3-13, 7-46 LCLS 3-13, 7-46 LTORG 7-14 MACRO 2-48, 7-27 MAP 2-51, 7-15 MEND 7-27, 7-46 MEXIT 7-29 nesting 7-26 NOFP 7-65 OPT 3-10, 7-46 REQUIRE 7-65, 7-66 RLIST 3-3, 7-8 RN 7-67 ROUT 2-13, 3-16, 3-17, 7-68 SETA 3-6, 3-10, 3-13, 7-7, 7-46 SETL 3-6, 3-10, 3-13, 7-7, 7-46 SETS 3-6, 3-10, 3-
Index LDM instruction 2-39, 2-54, 3-3, 7-8 Thumb 2-46 LDR pseudo-instruction 2-25, 2-27, 2-35, 4-82 Thumb pseudo-instruction 5-41 LDR pseudo-instruction 7-14 :LEFT: operator 3-28 :LEN: operator 3-26 Line format, assembly language 2-12 Line length, assembly language 2-12 Link register 2-5, 2-17 Linking assembly language labels 2-13 Literal pools, assembly language 2-28 Loading constants, assembly language 2-25 Local labels, assembly 3-16 variables, assembly 7-6, 7-7 Local labels, assembly language 2-13 Logi
Index Status flags 2-20 STM instruction 2-39, 2-54, 3-3, 7-8 Thumb 2-46 :STR: operator 3-26 String expressions, assembly 3-19 manipulation, assembly 3-28 variable, assembly 3-13 String constants, assembly language 2-14 String literals, assembly 3-19 Subroutines, assembly language 2-17 SUBT directive 7-48 Symbols assembly language 3-12 assembly language, Naming rules 3-12 Symbols, register-based 2-58 W WEAK symbol 7-60, 7-62 WEND directive 7-32 WHILE directive 7-29, 7-32 Symbols ! directive 7-45 # directi
Index Index-6 Copyright © 2000, 2001 ARM Limited. All rights reserved.
