Datasheet

ARMulator Basics

2.8.5 Configuring the map memory model

You can configure the map memory model to model several different types of memory

controller, by editing its entry in the

peripherals.ami

file:

{ Default_Mapfile=Mapfile

AMBABusCounts=False

;SpotISCyles=True|False

SpotISCyles=True

;ISTiming=Late|Early|Speculative

ISTiming=Late

}

Counting AMBA

™

decode cycles

You can configure the model to insert an extra decode cycle for every nonsequential

access from the processor. This models the decode cycle seen on some AMBA bus

systems. Enable this by setting

AMBABusCounts=True

peripherals.ami

Merged I-S cycles

All ARM processors, particularly cached processors, can perform a nonsequential

access as a pair of idle and sequential cycles, known as merged I-S cycles. By default,

the model treats these cycles as a nonsequential access, inserting wait states on the

S-cycle to lengthen it for the nonsequential access.

You can disable this by setting

SpotISCycles=False

peripherals.ami

. However, this is

likely to result in exaggerated performance figures, particularly when modeling cached

ARM processors.

The model can simulate merged I-S cycles using one of three strategies:

Speculative This models a system where the memory controller hardware

speculatively decodes all addresses on idle cycles. The controller can use

both the I- and S-cycles to perform the access. This results in one fewer

wait state.

Early This starts the decode when the ARM declares that the next cycle is going

to be an S-cycle, that is, half-way through the I-cycle. This can sometimes

result in one fewer wait states. (Whether or not there are fewer wait states

depends on the cycle time and the nonsequential access time for that

region of memory.)

This is the default setting. You can change this by setting

ISTiming=Spec

ISTiming=Late

peripherals.ami