Datasheet

ARMulator Basics

ARM940T PU

For an ARM940T, the PU is initialized as follows:

• The P, D, W, and I bits are set in the configuration register, register 1, to enable

the PU, the write buffer, the data cache and the instruction cache.

• Both the cacheable registers, register 2, are initialized to 1, marking region 0 as

cacheable for the I and D caches. This is displayed in the debugger as

0x0101

where:

— the low byte (bits 0..7) represent the data cache cacheable register

— the high byte (bits 8..15) represent the instruction cache cacheable register.

• The write buffer control register, register 3, is initialized to 1, marking region 0 as

bufferable. This applies only to the data cache. The instruction cache is read only.

• Both the protection registers, register 5, are initialized to 3, marking region 0 as

allowing full access for both instruction and data caches. This is displayed in the

debugger as

0x00030003

, where:

— the low halfword (bits 0..15) represent the data cache protection register

— the high halfword (bits 16..31) represent the instruction cache protection

The first register value shown is for region 0, the second for region 1 and so on.

• The protection region base and size register for regions 0 and 1 are initialized to

mark the sizes of the regions and mark them as enabled. The protection region

base and size registers for all regions are part of register 6. Register 6 is really a

set of sixteen registers, each being the protection region base and size register for

one region. See the data sheet for the processor for further details.

• Register 7 is a control register. Reading from it is unpredictable. At startup the

debugger shows a value of zero. It is not written to by the page table module.

• The programming lockdown registers, register 9, are both initialized to zero. The

first register value shown in the debugger is for data lockdown control, the second

is for instruction lockdown control.

• The test and debug register, register 15, is initialized to zero. Only bits 2 and 3

have any effect in ARMulator. These control whether the cache replacement

algorithm is random or round-robin.