Datasheet

ARMulator Basics
ARM DUI0058D Copyright © 1999-2001 ARM Limited. All rights reserved. 2-21
2.6.4 Memory regions
The rest of the Pagetables configuration section defines a set of memory regions. Each
region has its own set of properties.
By default,
peripherals.ami contains a description of a two regions:
{ Region[0]
VirtualBase=0
PhysicalBase=0
Size=4GB
Cacheable=No
Bufferable=No
Updateable=Yes
Domain=0
AccessPermissions=3
Translate=Yes
}
{ Region[1]
VirtualBase=0
PhysicalBase=0
Size=128Mb
Cacheable=Yes
Bufferable=Yes
Updateable=Yes
Domain=0
AccessPermissions=3
Translate=Yes
}
You can add more regions following the same general form:
Region[n] names the regions, starting with Region[0] . n is an integer.
VirtualBase applies only to a processor with an MMU. It gives the address of
the base of the region in the virtual address space of the processor.
This address must be aligned to a 1MB boundary. It is mapped to
PhysicalBase by the MMU.
PhysicalBase gives the physical address of the base of the region. On a processor
with an MMU, this address must be aligned to a 1MB boundary.
On a processor with a PU it must be aligned to a boundary that is
a multiple of the size of the region.
Size specifies the size of this region. On a processor with an MMU Size
must be a whole number of megabytes. On a processor with a PU,
Size must be 4KB or a power-of-two multiple of 4KB.