Datasheet

ARMulator Basics
2-18 Copyright © 1999-2001 ARM Limited. All rights reserved. ARM DUI0058D
2.5.6 strongARM1
Table 2-6 shows the meaning of cycle types reported for strongARM1.
2.5.7 Core-specific verbose statistics
There is a line in the
default.ami
file:
Counters=False
You can change this to read:
Counters=True
If you do this, additional statistics, such as cache hits and cache misses, are counted by
ARMulator and appear in
$statistics
. These statistics are core-specific.
Table 2-6 strongARM specific cycle types
Cycle types Meaning
Core_Idle No instruction fetched from instruction cache. No data fetched from data cache.
Core_IOnly Instruction fetched from instruction cache. No data fetched from data cache.
Core_DOnly No instruction fetched from instruction cache. Data fetched from data cache.
Core_ID Instruction fetched from instruction cache. Data fetched from data cache.