Datasheet

ARMulator Basics

2.5.4 Cached cores with MMUs or PUs and AMBA AHB interfaces

Table 2-4 shows the types of transfer that can occur on the Advanced High-speed Bus

(AHB). ARM946E-S, for example, is a cached core with an AHB interface. For

additional cycle types for these cores, see Internal cycle types for cached cores.

2.5.5 Internal cycle types for cached cores

Table 2-5 shows the meaning of internal cycle types for cached cores.

Note

If you want to count execution time, use external bus cycle counts (see Cached cores

with MMUs or PUs and AMBA ASB interfaces on page 2-16 or Cached cores with

MMUs or PUs and AMBA AHB interfaces). You cannot use F_Cycles to count

execution time, because F_Cycles does not increment for uncached accesses.

Table 2-4 Cycle types on AMBA AHB interfaces

Cycle types Meaning

IDLE The bus master does not want to use the bus. Slaves must respond with a zero wait state OKAY

response on HRESP.

BUSY The bus master is in the middle of a burst, but cannot proceed to the next sequential access.

Slaves must respond with a zero wait state OKAY response on HRESP.

NON-SEQ The start of a burst or single access. The address is unrelated to the address of the previous

access.

SEQ Continuing with a burst. The address is equal to the previous address plus the data size.

Table 2-5 Internal cycle types for cached cores

Cycle types Meaning

F_Cycles Fast clock (FLCK) cycles. These are internal core cycles accessing the cache. F_Cycles is

not incremented for uncached accesses because the core clock switches to the bus clock.

Core Cycles Core cycles are clock ticks to the core. Core Cycles are incremented for each tick, whether

the core is running FCLK (cache accesses) or bus clock (BCLK, non-cache accesses).

True Idle Cycles Idle cycles that are not part of a merged I-S cycle.