Datasheet

ARMulator Basics

2.5.2 Uncached Harvard cores

Table 2-2 shows the meanings of cycle types for uncached Harvard cores. ARM9TDMI,

for example, is an uncached Harvard core.

2.5.3 Cached cores with MMUs or PUs and AMBA ASB interfaces

Table 2-3 shows the meanings of the bus cycle types for cached cores with AMBA ASB

interfaces. For additional cycle types for these cores, see Internal cycle types for cached

cores on page 2-17.

ARM920T, for example, is a cached core with an MMU. ARM940T is an example of a

cached core with a PU.

There are no N_Cycles for these cores. Nonsequential accesses use an A_Cycle

followed by an S_Cycle. This is the same as a merged I-S cycle.

Table 2-2 Cycle type meanings for uncached Harvard cores

Cycle types Instruction bus Data bus Meaning

Core cycles - - The total number of ticks of the core clock. This includes pipeline

stalls due to interlocks and instructions that take more than one cycle.

ID_Cycles Active Active -

I_Cycles Active Idle -

Idle Cycles Idle Idle -

D_Cycles Idle Active -

Total - - The sum of core cycles, ID_Cycles, I_Cycles, Idle_Cycles,

D_Cycles, and Waits.

Table 2-3 Cycle type meanings for cached cores with AMBA ASB interfaces

Cycle types Meaning

A_Cycles An address is published speculatively. No data is transferred. Listed as I_Cycles in $statistics.

S_Cycles Sequential data is transferred from the current address.