Datasheet

ARMulator Basics

2.5.1 Uncached von Neumann cores

Table 2-1 shows the meanings of cycle types for uncached von Neumann cores.

ARM7TDMI, for example, is an uncached von Neumann core.

Sequential cycles

The CPU requests transfer to or from:

• the same address as the address accessed in the immediately preceding cycle

• an address that is one word after the address accessed in the immediately

preceding cycle

• for Thumb instruction fetches only, an address that is one half-word after the

address accessed in the immediately preceding cycle.

Merged I-S cycles

A memory controller can start speculatively decoding an address during an I-Cycle. If

the I_Cycle is followed by an S_Cycle, the memory controller can be ready to issue it

earlier than otherwise. The timing of this cycle depends on the memory controller

implementation.

Table 2-1 Cycle type meanings for uncached von Neumann cores

Cycle type

SEQ

signal

nMREQ

signal

Meaning

S_Cycles 1 1 Sequential cycles. See Sequential cycles for details.

N_Cycles 0 1 Nonsequential cycles. The CPU requests a transfer to or from an address

unrelated to the address used in the immediately preceding cycle.

I_Cycles 1 0 Internal cycles. The CPU does not require a transfer because it is

performing an internal function.

C_Cycles 0 0 Coprocessor cycles.

Total - - The sum of S_Cycles, N_Cycles, I_Cycles, C_Cycles, and Waits.

IS - - Merged I-S cycle. See Merged I-S cycles for details.