Datasheet

ARMulator Basics

2.5 ARMulator cycle types

In addition to simulating instruction execution on ARM cores, ARMulator counts bus

and processor cycles. You can access these counts as

$statistics

from your debugger.

This section describes the meaning of the various types of cycles counted. It contains

the following sections:

• Uncached von Neumann cores on page 2-15

• Uncached Harvard cores on page 2-16

• Cached cores with MMUs or PUs and AMBA ASB interfaces on page 2-16

• Cached cores with MMUs or PUs and AMBA AHB interfaces on page 2-17

• Internal cycle types for cached cores on page 2-17

• strongARM1 on page 2-18

• Core-specific verbose statistics on page 2-18.