Datasheet

ARMulator Basics
ARM DUI0058D Copyright © 1999-2001 ARM Limited. All rights reserved. 2-7
Trace memory (M lines)
M lines indicate:
• memory accesses, for cores without on-chip memory
• on-chip memory accesses, for cores with on-chip memory.
They have the following format for general memory accesses:
M<type><rw><size>[O][L][S] <address> <data>
where:
<type> indicates the cycle type:
S sequential
N nonsequential.
<rw> indicates either a read or a write operation:
R read
W write.
<size> indicates the size of the memory access:
4 word (32 bits)
2 halfword (16 bits)
1 byte (8 bits).
O indicates an opcode fetch (instruction fetch).
L indicates a locked access ( SWP instruction).
S indicates a speculative instruction fetch.
<address> gives the address in hexadecimal format, for example 00008008 .
<data> can show one of the following:
value gives the read/written value, for example EB00000C
(wait)
indicates nWAIT was LOW to insert a wait state
(abort) indicates ABORT was HIGH to abort the access.
Trace memory lines can also have any of the following formats:
MI for idle cycles
MC for coprocessor cycles
MIO for idle cycles on the instruction bus of Harvard architecture processors
such as ARM9TDMI
™
.