Datasheet

ARMulator Reference

Timer clear registers

Timer clear registers are write-only. Writing to one of them clears an interrupt generated

by the corresponding timer.

Timer control registers

See Table 4-14 and Table 4-13 for details of timer register bits. Only bits 7, 6, 3, and 2

are used. You must write all others as zeroes.

The counter counts downwards. It counts BCLK cycles, or BCLK cycles divided by 16

or 256. Bits 2 and 3 define the prescaling applied to the clock.

In free-running mode, the timer counter overflows when it reaches zero, and continues

to count down from

0xFFFF

In periodic mode, the timer generates an interrupt when the counter reaches zero. It then

reloads the value from the load register and continues to count down from this value.

Table 4-13 Clock prescaling using bits 2 and 3

Bit

Clock

divided by

Stages of

prescale

001 0

0116 4

10256 8

1 1 Undefined -

Table 4-14 Timer enable and mode control using bits 6 and 7

Bit 7 Timer disabled Timer enabled

Bit 6 Free-running

mode

Periodic mode