Datasheet

ARMulator Reference
4-76 Copyright © 1999-2001 ARM Limited. All rights reserved. ARM DUI0058D
Interrupt controller defined bits
The FIQ interrupt controller is one bit wide. It is located on bit 0.
Table 4-11 gives details of the interrupt sources associated with bits 1 to 5 in the IRQ
interrupt controller registers. You can use bit 0 for a duplicate FIQ input.
NoteNote
Timer 1 and Timer 2 can be configured to use different bits in the IRQ controller
registers, see Timer on page 2-34.
Table 4-11 Interrupt sources
Bit Interrupt source
0 FIQ source
1 Programmed interrupt
2 Communications channel Rx
3 Communications channel Tx
4Timer 1
5Timer 2