Datasheet

ARMulator Reference
ARM DUI0058D Copyright © 1999-2001 ARM Limited. All rights reserved. 4-75
4.16 Reference peripherals
Two reference peripherals are detailed here:
• Interrupt controller
• Timer on page 4-77.
4.16.1 Interrupt controller
The base address of the interrupt controller,
IntBase , is configurable (see Interrupt
controller on page 2-33).
Table 4-10 shows the location of individual registers.
Table 4-10 Interrupt controller memory map
Address Read Write
IntBase IRQStatus Reserved
IntBase + 004 IRQRawStatus Reserved
IntBase + 008 IRQEnable IRQEnableSet
IntBase + 00C Reserved IRQEnableClear
IntBase + 010 Reserved IRQSoft
IntBase + 100 FIQStatus Reserved
IntBase + 104 FIQRawStatus Reserved
IntBase + 108 FIQEnable FIQEnableSet
IntBase + 10C Reserved FIQEnableClear