Datasheet
C and C++ Compilers
2-26 Copyright © 1999-2001 ARM Limited. All rights reserved. ARM DUI 0067D
-Oautoinline
This option enables automatic inlining. It is off by default for
optimization levels
-O0
and
-O1
, and on by default for optimization level
-O2
. The compiler automatically inlines functions where it is sensible to
do so. The
-Ospace
and
-Otime
options influence how the compiler
automatically inlines functions.
-Ono_ldrd
This option disables optimizations specific to ARM Architecture v5TE
processors. This is the default.
-Ono_data_reorder
This option disables automatic reordering of top-level data items
(globals, for example). The C/C++ compilers save memory by
eliminating wasted space between data items. However, this optimization
can break legacy code, if the code (incorrectly) makes assumptions about
ordering of data by the compiler. The C standard does not guarantee data
order, so you must avoid writing code that depends on any assumed
ordering. If you require data ordering, place the data items into a
structure.
-Oldrd
This option enables optimizations specific to ARM Architecture v5TE
processors. If you select this option, and select an Architecture v5TE
-cpu
option such as
-cpu xscale
, the compiler:
• Generates
LDRD
and
STRD
instructions where appropriate.
• Sets the natural alignment of
double
and
long
long
variables to
eight. This is equivalent to specifying
__align(8)
for each variable.
Note
If you select this option, the output object is marked as requiring
8-byte alignment. This means that it is unlikely to link with objects
built with versions of ADS earlier than 1.1.
-split_ldm
This option instructs the compiler to split
LDM
and
STM
instructions into
two or more
LDM
or
STM
instructions, where required, to reduce the
maximum number of registers transferred to:
• five, for all
STM
s, and for
LDM
s that do not load the PC
• four, for
LDM
s that load the PC.
This option can reduce interrupt latency on ARM systems that:
• do not have a cache or a write buffer (for example, a cacheless
ARM7TDMI)
• use zero-wait-state, 32-bit memory.