Datasheet

Differences
ARM DUI 0064D Copyright © 1999-2001 ARM Limited. All rights reserved. 2-33
Note
BATS is no longer shipped with ADS 1.1 or later.
The compiler performs instruction scheduling for ARM10 code by re-ordering machine
instructions to gain maximum speed and minimize wait states. The linker uses
BLX
in
interworking veneers when the underlying architecture (the ARM9E and ARM10, for
example, have architecture 5) supports it.
New ARM/Thumb procedure call standard
The Procedure Call Standard has been redesigned to:
give equal emphasis to ARM and Thumb
interwork between ARM-state and Thumb-state for all variants
reduce the number of variants
support position-independence
produce compact code (especially with Thumb)
be binary compatible with the previous most commonly used APCS variant.
The new ARM/Thumb Procedure Call Standard (ATPCS) enables a consistent ARM
and Thumb definition of Read Only Position Independence (also called Position
Independent Code), and Read Write Position Independence (also called Position
Independent Data) for both ARM and Thumb.
Floating-point support
Enhanced floating-point support is available in the compiler, assembler, and debugger:
The compiler, assembler, and debugger support the new VFP floating-point
architecture in scalar mode.
The compiler can generate VFP instructions for
double
and
float
operations. (The
inline assembler, however, does not support VFP.)
The assembler supports VFP in vector mode. (New register names and directives
are available.)
The compiler and assembler command-line option
-fpu
specifies the FPA
hardware, VFP hardware, or software variants.
Choose
-fpu FPA
or
-fpu softFPA
to retain the old SDT 2.50/2.51 format.