Specifications

Specifications
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. B-6
ID052914 Non-Confidential
Figure B-5 Video multiplexer FPGA timing
The timing intervals are as follows:
• Video data, clocked by
MMB_IDCLK :
— Tis = 6.00ns.
— Tih = 0.00ns.
• Audio data, clocked by
MMB_MCLK :
— Tis = 5.30ns.
— Tih = 0.00ns.
• Audio data, clocked by
MMB_SCLK :
— Tis = 2.65ns.
— Tih = 0.00ns.
User LEDS
Video SRAM
NOR FLASH 0
User SRAM
USB
Ethernet
NOR FLASH 1
Compact
Flash
2 x KMI
SD/MMC
AACI
4 x UART
MMB Mux
Matrix, multiplexers,
and bridges
I/O FPGA
CS0
Peripherals
PCIe I2C
Motherboard
Configuration
Controller
Interrupts and
DMA control
DVI
CS3
CS4
CS1
CS2
CS2
CS2
CB
Site 1 Site 2Site 1 Site 2
SB_GCLK
MMB2 to
Site 2
MMB1 to
Site 1
SMB1 to
Site 1
SMB2 to
Site 2
MMB