Specifications

Specifications
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. B-2
ID052914 Non-Confidential
B.1 Timing specifications
This section provides the timing specifications for the SMB bus. These timing specifications are
required if you implement an SMB interface in a LogicTile Express daughterboard. All CoreTile
Express daughterboards correctly implement the timing requirements in this section.
B.1.1 SMB synchronous read
Figure B-1 shows the synchronous read timing.
Figure B-1 Synchronous read timing
The intervals are:
•
Tsmbis = 6ns.
•
Tsmbov = 7.5ns.
•
Tsmboh = Tperiod /2.
•
Toe_n = 1 cycle, minimum.
•
Trc_ncs7 = 5 cycles, minimum.
•
Trc_ncs3 = 7 cycles, minimum.
All signals are clocked off SMB_CLKO.
SMB_CLKI is transmitted by the IO FPGA, but it does not clock any data.
SMB_ADDR
ADDR
SMB_CLKO
Tsmbis
SMB_CLKI
RDATA
SMB_DATA
SMB_nOE
SMB_nCS
SMB_nWAIT
Wait_req_SMB_CLKI
Wait_req_SMB_CLKO
Trc
Tsmb
ov
Tsmboh
Tsmb
ov
Tsmbis
Toe_n
Tperiod
SMB_nADV