Specifications

Programmers Model
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-38
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Table 4-35 provides information about the UART interfaces.
The PrimeCell UART varies from the industry-standard 16C550 UART device as follows:
• UART0 has full handshaking signals, RTS, CTS, DSR, DTR, DCD, and RI, but DSR and
CTS are used for remote operation. See the ARM
®
Versatile
™
Express Configuration
Technical Reference Manual.
• Handshaking signals for UART1-3 consist of RTS and CTS.
• Receive FIFO trigger levels are 1/8, 1/4, 1/2, 3/4, and 7/8.
• The internal register map address space, and the bit function of each register differ.
• Information relating to the modem status signals are not available.
• 1.5 stop bits not available, 1 or 2 stop bits only are supported.
• No independent receive clock.
Table 4-35 UART implementation
Property Value
Location Motherboard IO FPGA
Memory base address • ARM Legacy memory map:
UART 0 SMB CS7 base address +
0x9000
UART 1 SMB CS7 base address + 0xA000
UART 2 SMB CS7 base address + 0xB000
UART 3 SMB CS7 base address + 0xC000 .
• Cortex-A Series memory map:
UART 0 SMB CS3 base address +
0x90000
UART 1 SMB CS3 base address + 0xA0000
UART 2 SMB CS3 base address + 0xB0000
UART 3 SMB CS3 base address + 0xC0000
UART 4 SMB CS3 base address + 0x1B0000 .
Interrupt • UART 0: 5
• UART 1: 6
• UART 2: 7
• UART 3: 8.
DMA mapping See Table 4-14 on page 4-18.
Note
You must set DMAPSR = b01 in the SYS_DMAPSR register to select this peripheral for
DMA access.
Release version ARM UART PL011 r1p3.
Platform Library support
_platform_uart_entry
Handles all channel operations for the UART channels, reading characters, writing
characters, and opening the channel.
Reference documentation PrimeCell UART (PL011) Technical Reference Manual.