Specifications

Programmers Model

ID052914 Non-Confidential

Table 4-29 provides information about the RTC.

Note

The motherboard Time-of-Year (TOY) clock updates the RTC on power-up. Any writes to the

RTC also update the TOY clock.

4.5.8 Two-wire serial bus interface, SBCon

The IO FPGA implements two custom two-wire serial bus interfaces, SBCon 0 and SBCon 1.

SBCon 0 provides access to the PCIe interface on the motherboard.

SBCon 1 provides access to the Digital Data Channel (DDC) of the external display connected

to the DVI connector on the rear panel.

The internal registers of the two-wire serial bus interface are memory-mapped onto a static

memory bus chip select. The chip select that they map onto depends on the memory map your

daughterboard is using as follows:

• ARM legacy memory map:

— The registers map onto the CS7 chip select.

• Cortex-A Series memory map:

— The registers map onto the CS3 chip select.

Note

See the Technical Reference Manual for your daughterboard.

Table 4-29 RTC implementation

Property Value

Location Motherboard IO FPGA

Memory base address • ARM Legacy memory map:

— SMB CS7 base address +

0x17000

• Cortex-A Series:

— SMB CS3 base address +

0x17000

Interrupt 4

DMA -

Release version ARM RTC PL031 r1p0

Reference documentation

ARM

PrimeCell Real Time Clock (PL031) Technical Reference Manual