Specifications
Programmers Model
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-28
ID052914 Non-Confidential
Table 4-23 provides information for the CLCDC.
The following locations are reserved, and must not be used during normal operation:
• Locations at offsets
0x030
to
0x1FE
are reserved for possible future extensions.
• Locations at offsets
0x400
to
0x7FF
are reserved for test purposes.
Note
• Different display resolutions require different data and synchronization timing.
OSCCLK1, 23.75MHz default, is assigned as CLCDCLK for the LCD controller. The
Post Screen has a 640x480 VGA 8-bit color pallet. Default display resolution is 1024x768
at a 60Hz frame rate. The default color depth is 16-bit. See the ARM
®
PrimeCell Color
LCD Controller (PL111) Technical Reference Manual for a description of the LCD timing
registers.
• The DVI controller display settings are configured with DVIMODE in the
config.txt
file.
See the ARM
®
Versatile
™
Express Configuration Technical Reference Manual or System
Configuration registers on page 4-21.
Display resolutions and display memory organization
Different display resolutions require different data and synchronization timing. Use registers
CLCD_TIM0, CLCD_TIM1, CLCD_TIM2, and OSCCLK1 to define the display timings.
The mapping of the 32 bits of pixel data in memory to the RGB display signals depends on the
resolution and the display mode.
For information on setting the red, green, and blue brightness for direct, non-palettized, 24-bit
and 16-bit color modes, see the ARM
®
PrimeCell Color LCD (PL111) Technical Reference
Manual. Self-test example code, that displays 24-bit and 16-bit VGA images, is also provided
on the accompanying DVD.
Note
For resolutions based on one to 16 bits per pixel, multiple pixels are encoded into each 32-bit
word.
All monochrome modes, and color modes using eight or fewer bits per pixel, use the palette to
encode the color value from the data bits. See the ARM
®
PrimeCell Color LCD (PL111)
Technical Reference Manual for information.
Table 4-23 CLCDC implementation
Property Value
Location Motherboard IO FPGA
Memory base address • ARM Legacy memory map:
— SMB CS7 base address +
0x1F000
.
•ARM Cortex-A Series memory map:
— SMB CS3 base address +
Ox1F0000
.
Interrupt 14
DMA -
Release version ARM CLCDC PL111, version r0p2.
Reference documentation
ARM
®
PrimeCell Color LCD Controller (PL111) Technical Reference Manual.