Specifications

Programmers Model
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-27
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Figure 4-15 AACI ID Register bit assignments
Table 4-22 shows the register bit assignments.
4.5.2 Color LCD Controller
The motherboard PL111 PrimeCell Color LCD Controller (CLCDC) is an AMBA-compliant
SoC peripheral that is developed, tested, and licensed by ARM.
The CoreTile Express daughterboard typically has a higher-performance CLCD controller. This
controller is in the IO FPGA and is intended for use with daughterboards that do not contain
their own CLCD controller.
031 78
Undefined
5623
FIFO depth
Number of channels
Reserved
Table 4-22 Modified AACI PeriphID3 Register bit assignments
Bit Access Name Description
[31:8] Write as zeros, read is undefined - Undefined
[7:6] Read-modify-write to preserve value Reserved Reserved
[5:3] Read-only FIFO depth FIFO depth in compact mode:
b000 4.
b001 16.
b010 32.
b011 64.
b100 128.
b101 256, default.
b110 512.
b111 1024.
[2:0] Read-only Number of channels Number of channels:
b000 4.
b001 1, default.
b010 2.
b011 3.
b100 4.
b101 5.
b110 6.
b111 7.