Specifications

Programmers Model
ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-9
ID052914 Non-Confidential
0x0058 SYS_CFGSW
RO/RW
a
0x000000XX
b
Bits [7:0] are the soft configuration switches. See Config Switch
Register on page 4-15.
0x005C SYS_24MHZ RO
0xXXXXXXXX
b
32-bit counter clocked at 24MHz. See 24MHz Counter Register on
page 4-16.
0x0060 SYS_MISC
RO/RW
a
0xXX0X0000
b
Miscellaneous control flags. See Miscellaneous Flags Register on
page 4-16.
0x0064 SYS_DMA RW 0x00000000 See DMA Channel Selection Register on page 4-17.
0x0068 –
0x0080
Reserved RO 0x00000000 -
0x0084 SYS_PROCID0 RW
0x0X000XXX
b
See SYS_ PROCID0 Register on page 4-18.
0x0088 SYS_PROCID1 RW
0x0X000XXX
b
See SYS_PRODCID1 Register on page 4-19.
0x008C –
0x009C
Reserved RW 0x00000000 -
0x00A0 SYS_CFGDATA RW 0x00000000 See System Configuration registers on page 4-21.
0x00A4 SYS_CFGCTRL RW 0x00000000 See Configuration Control Register on page 4-22.
0x00A8 SYS_CFGSTAT RW 0x00000000 See Configuration Status Register on page 4-24
0x00AC –
0x0FFF
Reserved RW 0x00000000 -
a. Where the register contains both Read Only and Read Write bits, see register.
b. Where
X = unknown at reset, or depending on build, see register.
Table 4-3 Register map for status and system registers (continued)
Offset
Value
Register Type Reset Description